FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-02-04 07:12:56 +08:00
Code Issues Releases Wiki Activity
70 Commits 1 Branch 0 Tags
Commit Graph

3 Commits

Author SHA1 Message Date
Konstantin Pavlov
7f1454e6f7 Updated TCL scripts 2019-07-28 12:26:13 +03:00
Konstantin Pavlov
51951d842d Added classic TAN timing analizer report parsing 2019-04-16 04:44:25 +03:00
Konstantin Pavlov
8c420a1570 Updated reporting script to write total ompilation time 2019-04-15 02:24:31 +03:00