FPGA/basic_verilog
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3 Commits

Author SHA1 Message Date
Konstantin Pavlov
2845a2a836 Updated lifo module to support FWFT and normal modes 2021-07-06 14:15:35 +03:00
Konstantin Pavlov (fm)
6b22c900b1 Updated EdgeDetect module instantiation 2018-12-07 11:26:03 +03:00
Konstantin Pavlov
2282e26c1f Added single-clock FIFO and LIFO buffer modules 2018-07-29 08:27:30 +03:00