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Author SHA1 Message Date
Konstantin Pavlov
4682b7e4d5 Added adder_tree module and testbench 2019-12-13 13:26:07 +03:00
Konstantin Pavlov
8936cd36e6 Updated delay module to support LENGTH=0 2019-12-13 13:23:54 +03:00
Konstantin Pavlov
21f4580a78 Updated SR trigger variation modules 2019-12-13 13:19:49 +03:00
Konstantin Pavlov
51f484b204 Restored testbenches 2019-11-15 15:35:41 +03:00
Konstantin Pavlov
7c9acbfbf0 Added pulse_stretch.sv and testbench 2019-11-15 15:32:26 +03:00
Konstantin Pavlov
99eaebc08a Deleted obsolete files 2019-11-14 12:26:14 +03:00
Konstantin Pavlov
7dec15cfe5 Added pulse_stretch.sv module 2019-11-14 12:22:18 +03:00
Konstantin Pavlov
0f33c1da67 Added module to convert data from big-endian to little-endian and back 2019-10-17 10:48:49 +03:00
Konstantin Pavlov
7bd8c659f3 Added module to pack Verilog-2001 arrays 2019-10-17 10:47:51 +03:00
Konstantin Pavlov
6b99e1fdab Added script to program Altera/Intel devices 2019-10-02 13:40:27 +03:00
Konstantin Pavlov
928bced8b1 Added iverilog-gtlwave simulation script for Windows 2019-09-30 01:33:19 +03:00
Konstantin Pavlov
a733fc5382 Added leave_one_hot module 2019-07-28 14:08:17 +03:00
Konstantin Pavlov
7f1454e6f7 Updated TCL scripts 2019-07-28 12:26:13 +03:00
Konstantin Pavlov
c77026f2bf Removed obsolete files 2019-06-28 03:23:04 +03:00
Konstantin Pavlov
066fd2f5dc Added Vivado post-flow script boilerplate 2019-06-28 03:18:13 +03:00
Konstantin Pavlov
306259c45f Added module to switch dims in a 2D systemverilog array 2019-06-28 01:31:19 +03:00
Konstantin Pavlov
3474f7b505 Updated dynamic_delay to allow delays bit-wize, not just element-wize 2019-06-28 01:28:45 +03:00
Konstantin Pavlov
431d06145b Added SIMULATION define to the testbench template 2019-05-24 14:23:19 +03:00
Konstantin Pavlov
5a05b4df56 Added helper script to launch and initialize system console 2019-05-24 14:16:41 +03:00
Konstantin Pavlov
6e6b4905c5 Renaming scripts 2019-05-24 14:14:43 +03:00
Konstantin Pavlov
7399deb17d Added Avalon master templates 2019-05-24 14:03:34 +03:00
Konstantin Pavlov
5bde0a502e Added version generating script to example project 2019-04-16 04:46:38 +03:00
Konstantin Pavlov
cd16cc5f9c Auto-incrementing project version for Quartus IDE 2019-04-16 04:45:23 +03:00
Konstantin Pavlov
51951d842d Added classic TAN timing analizer report parsing 2019-04-16 04:44:25 +03:00
Konstantin Pavlov
6bdafa6d56 Added errors supression script for Vivado to allow 'proto' projects w/o pin assignments 2019-04-16 04:42:39 +03:00
Konstantin Pavlov
1fdc31ad05 Added quartus benchmarking project 2019-04-15 02:37:45 +03:00
Konstantin Pavlov
8c420a1570 Updated reporting script to write total ompilation time 2019-04-15 02:24:31 +03:00
Konstantin Pavlov
57de1109bc Selector width fixed in dynamic_delay.sv 2019-04-14 00:07:00 +03:00
Konstantin Pavlov
b6028753ef Minor tcl script fixes 2019-03-30 18:16:28 +03:00
Konstantin Pavlov
80bcda370b Added a bunch of TCL scripts 2019-03-30 18:01:20 +03:00
Konstantin Pavlov
bea7cad324 Added quick shortcut for Modelsim compilation 2019-03-11 00:10:07 +03:00
Konstantin Pavlov
fe43d58156 Drastically simplyfied universal SPI master 2019-03-11 00:08:56 +03:00
Konstantin Pavlov
fbb6ecff17 Added System Console initialization script 2019-03-10 21:05:01 +03:00
Konstantin Pavlov
732a6883d5 Added scripts directory. Added SOF to RBF converter 2019-03-10 20:35:09 +03:00
Konstantin Pavlov
0b8a793478 Fixed delay length 2019-02-27 15:08:26 +03:00
Konstantin Pavlov
2713e374c1 Lots of minor edits 2019-02-23 00:20:06 +03:00
Konstantin Pavlov
f04430c7a8 Added universal spi master module 2019-02-22 23:33:58 +03:00
Konstantin Pavlov (fm)
f8794b5c48 Added Modelsim compile TCL script 2019-02-11 11:39:06 +03:00
Konstantin Pavlov (fm)
9c1670a472 Added sample asynchronous external device logic 2019-02-08 13:56:50 +03:00
Konstantin Pavlov (fm)
8e61fc2036 Added initialization for testbench clocks and resets 2019-01-29 13:24:06 +03:00
Konstantin Pavlov (fm)
cb280f51cf Fixed RS triggers declaration syntax 2019-01-09 15:12:55 +03:00
Konstantin Pavlov (fm)
ba53bc5486 Updated SystemVerilog variants of delay modules 2019-01-09 14:59:39 +03:00
Konstantin Pavlov (fm)
a6280adfde Added SystemVerilog version of clock divider 2019-01-09 14:38:52 +03:00
Konstantin Pavlov (fm)
d971d108cf Removed obsolete delay modules 2019-01-09 14:34:45 +03:00
Konstantin Pavlov (fm)
a66013eb1c Removed obsolete RS trigger modules 2019-01-09 14:33:13 +03:00
Konstantin Pavlov (fm)
2d8e67db35 snake_case for reverse_vector module and its testbench 2019-01-09 14:32:02 +03:00
Konstantin Pavlov (fm)
842496f0da Updated SystemVerilog variants of SR trigger featuring dominant logic state 2019-01-09 14:28:29 +03:00
Konstantin Pavlov (fm)
d39ccb2dd7 Added paramater to instantiation template of delay.sv 2019-01-09 14:23:45 +03:00
Konstantin Pavlov (fm)
807cc4303d Added .ena input to delay.sv 2019-01-09 13:58:20 +03:00
Konstantin Pavlov (fm)
6d933d2ea2 snake_case naming for clock divider and main testbench template 2018-12-11 15:42:09 +03:00