FPGA/basic_verilog
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16 Commits

Author SHA1 Message Date
Konstantin Pavlov
66ff427e1e Added error suppression for Modelsim script 2022-04-25 01:03:37 +03:00
Konstantin Pavlov
322fa85652 Updated test projects to support dev boards 2022-04-05 18:35:04 +03:00
Konstantin Pavlov
a928a6c326 Updated Vivado test project to v2. Digilent Arty board does supported now 2022-03-30 19:40:12 +03:00
Konstantin Pavlov
4c6c8eabb7 Minor fixes for Quartus test project 2022-03-30 19:28:46 +03:00
Konstantin Pavlov
6c5ef366e7 Added Vivado quick project template 2021-11-01 14:48:05 +03:00
Konstantin Pavlov
b87a6bfad0 Added testbench template 2021-11-01 14:47:08 +03:00
Konstantin Pavlov
aa52420d17 Updated Quartus Makefile and the reference project 2021-04-12 12:45:55 +03:00
Konstantin Pavlov
111dbc65c6 Test project for iterative compilation Quartus projects 2021-02-05 16:13:27 +03:00
Konstantin Pavlov
cf3b4f5d20 Moved all bencmarks to the separate directory 2021-01-26 15:16:11 +03:00
Konstantin Pavlov
68922a34d2 Updated benchmark projects. Added 'benchmark_results.txt' that i got on my machine 2020-12-17 18:42:52 +03:00
Konstantin Pavlov
d44ef08c2c Added benchmark project for Xilinx ISE Design Suite 2020-12-17 17:58:16 +03:00
Konstantin Pavlov
8980f487e9 Added benchmark project for Gowin FPGAs 2020-12-11 13:49:16 +03:00
Konstantin Pavlov
573cc6e6b8 Added benchmark project for Vivado IDE 2020-04-07 14:29:25 +03:00
Konstantin Pavlov
8db4b773b9 Added test project template 2020-02-27 20:40:08 +03:00
Konstantin Pavlov
5bde0a502e Added version generating script to example project 2019-04-16 04:46:38 +03:00
Konstantin Pavlov
1fdc31ad05 Added quartus benchmarking project 2019-04-15 02:37:45 +03:00