FPGA/basic_verilog
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2 Commits

Author SHA1 Message Date
Konstantin Pavlov
58c10b0fcb Added hex2ascii as a standalone module 2023-02-19 01:47:14 +03:00
Konstantin Pavlov
68b33a10d4 Added simple UART logger 2022-04-23 04:29:15 +03:00