FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-28 07:02:55 +08:00
Code Issues Releases Wiki Activity
104 Commits 1 Branch 0 Tags
Commit Graph

2 Commits

Author SHA1 Message Date
Konstantin Pavlov
573cc6e6b8 Added benchmark project for Vivado IDE 2020-04-07 14:29:25 +03:00
Konstantin Pavlov
1fdc31ad05 Added quartus benchmarking project 2019-04-15 02:37:45 +03:00