FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-14 06:42:54 +08:00
Code Issues Releases Wiki Activity
262 Commits 1 Branch 0 Tags
Commit Graph

2 Commits

Author SHA1 Message Date
Konstantin Pavlov
f7ad55c7fa Added typed versions of slicer functions 2023-10-25 04:17:06 +03:00
Konstantin Pavlov
014b8c53e2 Done slicer functions as a parametrized SV class 2023-10-20 01:04:13 +03:00