FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-28 07:02:55 +08:00
Code Issues Releases Wiki Activity
127 Commits 1 Branch 0 Tags
Commit Graph

2 Commits

Author SHA1 Message Date
Konstantin Pavlov
536a8b83d2 Rewriting UART modules to SystemVerilog 2021-01-26 15:30:56 +03:00
Konstantin Pavlov (pt)
ee9d1b9e66 Added UART receiver and transmitter modules 2016-03-30 21:33:41 +03:00