FPGA/basic_verilog
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3 Commits

Author SHA1 Message Date
Konstantin Pavlov
f74126e5d6 Minor style fixes 2022-05-01 14:50:23 +03:00
Konstantin Pavlov
e3cba6a4f6 Changed reset mode to asynchronous for soft_latch.sv 2022-03-31 15:36:38 +03:00
Konstantin Pavlov
1efbd7c243 Added soft_latch module and testbench 2021-07-09 17:24:20 +03:00