FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-14 06:42:54 +08:00
Code Issues Releases Wiki Activity
140 Commits 1 Branch 0 Tags
Commit Graph

10 Commits

Author SHA1 Message Date
Konstantin Pavlov
002db3191e Added dalayed_event module 2020-10-30 11:40:27 +03:00
Konstantin Pavlov
aa1ac56e14 Added ALTERA_TAPS delay type 2020-07-16 16:33:04 +03:00
Konstantin Pavlov
b57c3a9ceb Updated delay module. Added block RAM implementation 2020-07-09 16:14:28 +03:00
Konstantin Pavlov
8936cd36e6 Updated delay module to support LENGTH=0 2019-12-13 13:23:54 +03:00
Konstantin Pavlov
431d06145b Added SIMULATION define to the testbench template 2019-05-24 14:23:19 +03:00
Konstantin Pavlov
0b8a793478 Fixed delay length 2019-02-27 15:08:26 +03:00
Konstantin Pavlov
2713e374c1 Lots of minor edits 2019-02-23 00:20:06 +03:00
Konstantin Pavlov (fm)
ba53bc5486 Updated SystemVerilog variants of delay modules 2019-01-09 14:59:39 +03:00
Konstantin Pavlov (fm)
d39ccb2dd7 Added paramater to instantiation template of delay.sv 2019-01-09 14:23:45 +03:00
Konstantin Pavlov (fm)
807cc4303d Added .ena input to delay.sv 2019-01-09 13:58:20 +03:00