FPGA/basic_verilog
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3 Commits

Author SHA1 Message Date
Konstantin Pavlov (pt)
0000b487e1 Uniform instantiation templates. Synch() renamed to StaticDelay() 2016-12-12 11:41:56 +03:00
Konstantin Pavlov (pt)
a045839afd Added extreme minimal UART implementations. Testing in progress 2016-04-07 13:42:47 +03:00
Konstantin Pavlov (pt)
ee9d1b9e66 Added UART receiver and transmitter modules 2016-03-30 21:33:41 +03:00