FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-14 06:42:54 +08:00
Code Issues Releases Wiki Activity
210 Commits 1 Branch 0 Tags
Commit Graph

210 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Konstantin Pavlov
f5f3d32951 Fixes for delayed_event module 2020-11-03 11:23:37 +03:00
Konstantin Pavlov
2d2041a663 Fixed usedw[] calculations in preview_fifo. Other minor fixes 2020-10-30 11:51:59 +03:00
Konstantin Pavlov
eb69a3a374 Added project archieving for Quartus post-flow script 2020-10-30 11:48:19 +03:00
Konstantin Pavlov
002db3191e Added dalayed_event module 2020-10-30 11:40:27 +03:00
Konstantin Pavlov
3ddb800544 Updated preview_fifo to support two word writes 2020-08-09 01:08:56 +03:00
Konstantin Pavlov
aa1ac56e14 Added ALTERA_TAPS delay type 2020-07-16 16:33:04 +03:00
Konstantin Pavlov
b57c3a9ceb Updated delay module. Added block RAM implementation 2020-07-09 16:14:28 +03:00
Konstantin Pavlov
d2f436d5dc Added preview FIFO testbench 2020-07-09 16:09:20 +03:00
Konstantin Pavlov
d07d0ad5f4 Added preview FIFO 2020-07-09 16:02:57 +03:00
Konstantin Pavlov
bb246b3568 Updated edge_detect to v.3 2020-05-22 15:59:50 +03:00
Konstantin Pavlov
ea6833b63e Added DSE launch script 2020-05-22 14:47:06 +03:00
Konstantin Pavlov
05fd57f2b8 Added Quartus project cleaning script 2020-05-22 11:45:23 +03:00
Konstantin Pavlov
c2ec8d320d Added testbench screenshots 2020-05-06 03:56:30 +03:00
Konstantin Pavlov
e68483d99a Added PDM modulator 2020-05-06 03:52:20 +03:00
Konstantin Pavlov
380f3a1f14 Added PWM modulator module and a testbench 2020-05-05 06:52:51 +03:00
Konstantin Pavlov
d5030cfb5d Updated pulse_gen to ver.2 2020-05-05 06:51:23 +03:00
Konstantin Pavlov
eba4111ce1 Added JTAG server setup script 2020-04-23 18:03:21 +03:00
Konstantin Pavlov
ec0bdd4948 Minor fixes 2020-04-16 10:57:36 +03:00
Konstantin Pavlov
4da5e8bc96 Updated readme 2020-04-07 22:33:24 +03:00
Konstantin Pavlov
d82a3bc050 Merge branch 'master' of https://github.com/pConst/basic_verilog 2020-04-07 15:36:51 +03:00
Konstantin Pavlov
8d3ea380a9 added script to set project directory in Vivado 2020-04-07 14:30:32 +03:00
Konstantin Pavlov
573cc6e6b8 Added benchmark project for Vivado IDE 2020-04-07 14:29:25 +03:00
Konstantin Pavlov
1840a5a8ca Updated post flow script for Vivado 2020-04-07 14:14:19 +03:00
Konstantin Pavlov
ff356f13e0 Two random generators with different seed values 2020-02-28 17:55:54 +03:00
Konstantin Pavlov
8db4b773b9 Added test project template 2020-02-27 20:40:08 +03:00
Konstantin Pavlov
f1604e8736 Added gray code converters 2020-02-25 15:38:56 +03:00
Konstantin Pavlov
b8064ecef9 Fixed header info in some testbenches 2020-02-25 15:38:02 +03:00
Konstantin Pavlov
c189b88688 Added PRBS test sequence generator and chekker 2020-02-11 15:34:00 +03:00
Konstantin Pavlov
8fa82449ed Added more scripts for Quartus IDE 2020-02-07 02:35:04 +03:00
Konstantin Pavlov
4150134587 Added pulse generator module 2020-02-07 02:28:00 +03:00
Konstantin Pavlov
4682b7e4d5 Added adder_tree module and testbench 2019-12-13 13:26:07 +03:00
Konstantin Pavlov
8936cd36e6 Updated delay module to support LENGTH=0 2019-12-13 13:23:54 +03:00
Konstantin Pavlov
21f4580a78 Updated SR trigger variation modules 2019-12-13 13:19:49 +03:00
Konstantin Pavlov
51f484b204 Restored testbenches 2019-11-15 15:35:41 +03:00
Konstantin Pavlov
7c9acbfbf0 Added pulse_stretch.sv and testbench 2019-11-15 15:32:26 +03:00
Konstantin Pavlov
99eaebc08a Deleted obsolete files 2019-11-14 12:26:14 +03:00
Konstantin Pavlov
7dec15cfe5 Added pulse_stretch.sv module 2019-11-14 12:22:18 +03:00
Konstantin Pavlov
0f33c1da67 Added module to convert data from big-endian to little-endian and back 2019-10-17 10:48:49 +03:00
Konstantin Pavlov
7bd8c659f3 Added module to pack Verilog-2001 arrays 2019-10-17 10:47:51 +03:00
Konstantin Pavlov
6b99e1fdab Added script to program Altera/Intel devices 2019-10-02 13:40:27 +03:00
Konstantin Pavlov
928bced8b1 Added iverilog-gtlwave simulation script for Windows 2019-09-30 01:33:19 +03:00
Konstantin Pavlov
a733fc5382 Added leave_one_hot module 2019-07-28 14:08:17 +03:00
Konstantin Pavlov
7f1454e6f7 Updated TCL scripts 2019-07-28 12:26:13 +03:00
Konstantin Pavlov
c77026f2bf Removed obsolete files 2019-06-28 03:23:04 +03:00
Konstantin Pavlov
066fd2f5dc Added Vivado post-flow script boilerplate 2019-06-28 03:18:13 +03:00
Konstantin Pavlov
306259c45f Added module to switch dims in a 2D systemverilog array 2019-06-28 01:31:19 +03:00
Konstantin Pavlov
3474f7b505 Updated dynamic_delay to allow delays bit-wize, not just element-wize 2019-06-28 01:28:45 +03:00
Konstantin Pavlov
431d06145b Added SIMULATION define to the testbench template 2019-05-24 14:23:19 +03:00
Konstantin Pavlov
5a05b4df56 Added helper script to launch and initialize system console 2019-05-24 14:16:41 +03:00
Konstantin Pavlov
6e6b4905c5 Renaming scripts 2019-05-24 14:14:43 +03:00