FPGA/basic_verilog
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  • bfed5f51c7 Add iperf test script master Konstantin Pavlov 2024-11-07 22:07:19 +03:00
  • a7e769108c Add barrel shifter Konstantin Pavlov 2024-07-06 10:58:53 +03:00
  • 2a75d7d8bf Updated RAM templates Konstantin Pavlov 2024-07-03 23:53:55 +03:00
  • 34e0e28b3c Add branches_to_directories script Konstantin Pavlov 2024-07-02 16:09:56 +03:00
  • e1412c080b Change some pins to I and IO for convinience Konstantin Pavlov 2024-07-02 16:01:04 +03:00
  • 955efdf32d
         Update benchmark_results.txt Konstantin Pavlov 2024-06-27 09:33:04 +03:00
  • d61338a4d3 Add missed IPs Konstantin Pavlov 2024-05-28 10:30:29 +03:00
  • 89b8dc6a3f Fixed Vivado gitignore Konstantin Pavlov 2024-05-28 10:28:40 +03:00
  • 0369dc0e8f
         Update benchmark_results.txt Konstantin Pavlov 2024-05-16 14:13:14 +03:00
  • 9f1f51c971
         Update benchmark_results.txt Konstantin Pavlov 2024-05-16 11:57:53 +03:00
  • 098067e1b0
         Update benchmark_results.txt Konstantin Pavlov 2024-05-16 11:46:11 +03:00
  • ccf136a5b9 Added opt scripts for Vivado Konstantin Pavlov 2024-03-12 17:52:08 +03:00
  • 4eae34a978 Added freq_meter module Konstantin Pavlov 2023-12-15 00:13:23 +03:00
  • aec03d4507 Added 8b10b encoder/decoder Konstantin Pavlov 2023-12-06 02:41:58 +03:00
  • 46e79a0d34 Added Wishbone interface Konstantin Pavlov 2023-10-29 13:57:06 +03:00
  • 4f10b2ad3d Add AXI interface definitions Konstantin Pavlov 2023-10-25 07:01:25 +03:00
  • f7ad55c7fa Added typed versions of slicer functions Konstantin Pavlov 2023-10-25 04:17:06 +03:00
  • 014b8c53e2 Done slicer functions as a parametrized SV class Konstantin Pavlov 2023-10-20 01:04:13 +03:00
  • 276aea1e87 Add packed array slicers Konstantin Pavlov 2023-10-18 08:39:40 +03:00
  • 64e0408e0c Added dsp_everywhere Konstantin Pavlov 2023-10-08 12:07:57 +03:00
  • 5020e0b13e Add combinational repeater module Konstantin Pavlov 2023-09-26 05:51:19 +03:00
  • 39c1b4cf02 Restored simplified Verilog version of edge_detect Konstantin Pavlov 2023-09-12 18:37:39 +03:00
  • 213e17c657 Add simple UDP Ethernet packet generator Konstantin Pavlov 2023-05-23 13:07:08 +03:00
  • bb0897a409 Fix clog usage in pulse_stretch.sv Konstantin Pavlov 2023-05-23 11:49:24 +03:00
  • f0edcd3af0 Update formatting Konstantin Pavlov 2023-05-23 11:30:21 +03:00
  • 0475ea0398 Fix typo Konstantin Pavlov 2023-05-23 11:12:22 +03:00
  • b81fda635d Fixed out[] initialization Konstantin Pavlov 2023-05-22 13:53:54 +03:00
  • 71303a0823 Updated delayed_event testbench Konstantin Pavlov 2023-05-22 13:46:06 +03:00
  • 8043f65f2b Added info banner Konstantin Pavlov 2023-05-22 13:44:20 +03:00
  • 23709d8278 Generalized delayed_event code Konstantin Pavlov 2023-05-22 13:41:44 +03:00
  • 2e3551056b Updated debounce Konstantin Pavlov 2023-05-22 13:39:56 +03:00
  • 0a7385391a Added modelsim / questasim error code cat Konstantin Pavlov 2023-05-17 13:07:48 +03:00
  • 9d51a2b2d2 Upd clogb2 info Konstantin Pavlov 2023-04-25 15:24:36 +03:00
  • 93bb8db9b8 Added sample code Konstantin Pavlov 2023-03-29 13:07:39 +03:00
  • 319de86e86 Add scripts Konstantin Pavlov 2023-03-27 14:18:58 +03:00
  • 454f71e80e HLS template project and scripts update Konstantin Pavlov 2023-03-12 21:09:32 +03:00
  • 8b1b2ef6a3 Added ASCII-to-HEX Konstantin Pavlov 2023-03-12 20:51:10 +03:00
  • eb72143194 README update Konstantin Pavlov 2023-03-12 20:50:32 +03:00
  • 3aa56798bd README update Konstantin Pavlov 2023-02-24 06:02:27 +03:00
  • d046210740 Added Vitis HLS scripts and example Konstantin Pavlov 2023-02-24 06:01:53 +03:00
  • baea1069cb Updated Gray functions Konstantin Pavlov 2023-02-24 05:59:40 +03:00
  • 0523320552 CP script update Konstantin Pavlov 2023-02-19 01:48:43 +03:00
  • 58c10b0fcb Added hex2ascii as a standalone module Konstantin Pavlov 2023-02-19 01:47:14 +03:00
  • 45a1621a4a Restored simplified Verilog version of delay.sv Konstantin Pavlov 2023-02-19 01:45:44 +03:00
  • db681a4efe Pattern is being detected in any bit position now Konstantin Pavlov 2023-02-06 02:10:12 +03:00
  • fd3835448a Added prog script Konstantin Pavlov 2022-12-29 17:16:39 +03:00
  • 11ca69c348 Fixed Questa support in testbench_template Konstantin Pavlov 2022-12-29 16:42:27 +03:00
  • 88db449245 Added updater script Konstantin Pavlov 2022-12-14 15:01:42 +03:00
  • 978bed92bc KCPSM dir gitignore Konstantin Pavlov 2022-12-14 14:00:14 +03:00
  • 06c2498504 Added xilinx board store Konstantin Pavlov 2022-12-14 13:59:33 +03:00
  • bdfd79b542 Updated scripts Konstantin Pavlov 2022-12-14 13:58:09 +03:00
  • 50300add8a Added clean scripts .. Konstantin Pavlov 2022-12-12 03:26:08 +03:00
  • ff72cd4ff6 Added clean scripts Konstantin Pavlov 2022-12-12 03:23:58 +03:00
  • de068b7426 Removed obsolete files Konstantin Pavlov 2022-12-12 03:19:02 +03:00
  • c06a419792 Updated test prj up to Vivado 2021.2 Konstantin Pavlov 2022-12-12 03:10:17 +03:00
  • 72cb6ac1d2 More submodules Konstantin Pavlov 2022-12-09 16:02:14 +03:00
  • b93545503e Added fresh submodule Konstantin Pavlov 2022-12-02 17:32:23 +03:00
  • f894f0997d Add more stats Konstantin Pavlov 2022-11-16 17:42:14 +03:00
  • 257c7fdff7 Fix template typo, 'block' paramerer is default Konstantin Pavlov 2022-11-16 17:07:08 +03:00
  • 65e4657650 Minor fix for read_ahead_buf Konstantin Pavlov 2022-11-11 15:51:08 +03:00
  • a9f7d50998 Added new benchmarks Konstantin Pavlov 2022-11-11 14:49:31 +03:00
  • 553e74c437 Updated Vivado gitignore Konstantin Pavlov 2022-11-11 14:29:24 +03:00
  • f9cfe3935b Added XPM sources Konstantin Pavlov 2022-11-10 11:07:17 +03:00
  • da92eddd80 Added swap script Konstantin Pavlov 2022-11-10 10:28:22 +03:00
  • 2543bcd567 Added scripts Konstantin Pavlov 2022-08-24 12:42:56 +03:00
  • 3d0bb13dda Updated Vivado gitignore Konstantin Pavlov 2022-07-29 13:50:45 +03:00
  • b1c07c9c5f Added Verilog versions of UART components Konstantin Pavlov 2022-07-12 20:03:13 +03:00
  • 0d9f67ff80 Updated testbench template Konstantin Pavlov 2022-07-03 16:39:54 +03:00
  • 5abae5370e Update Modelsim gitignore Konstantin Pavlov 2022-07-03 16:38:37 +03:00
  • 65c465506b Updated tb template with clock gen module Konstantin Pavlov 2022-06-19 20:18:37 +03:00
  • 6d98d9d93a Added configurable simulation clock gen Konstantin Pavlov 2022-06-19 20:17:44 +03:00
  • 49fefc9bf0 Straight and simple realization of recursive scripts Konstantin Pavlov 2022-06-16 06:59:32 +03:00
  • 783c33e268 Updated testbench template project Konstantin Pavlov 2022-06-16 06:57:56 +03:00
  • 8f32dd53d9 Added pattern detector and tb Konstantin Pavlov 2022-06-16 06:56:45 +03:00
  • 24fbb6c3d3 Added optional filtering Konstantin Pavlov 2022-06-06 09:53:55 +03:00
  • f7c4995847 Added fifo combiner Konstantin Pavlov 2022-06-06 09:53:15 +03:00
  • b8af169ee5 Updated scripts Konstantin Pavlov 2022-06-06 09:52:10 +03:00
  • 2388fd3d54 Removed obsolete files. Updated scripts Konstantin Pavlov 2022-06-01 17:53:44 +03:00
  • 5bba1d2b7e Updated Vivado clean script Konstantin Pavlov 2022-05-20 21:36:55 +03:00
  • e583c9f977 Added reference souce code dir Konstantin Pavlov 2022-05-16 19:44:36 +03:00
  • 864a6900b9 More README fixes Konstantin Pavlov 2022-05-16 19:39:38 +03:00
  • 8d569ce7a1 Fixed READMEs Konstantin Pavlov 2022-05-16 19:29:41 +03:00
  • 66733fa819 Added benchmark_projects dir README Konstantin Pavlov 2022-05-16 19:21:43 +03:00
  • f6a5726184 Added reference benchmark project for Gowin IDE Konstantin Pavlov 2022-05-16 19:06:38 +03:00
  • 68ec41121e Added gitignore and clen script for Gowin IDE projects Konstantin Pavlov 2022-05-16 18:58:36 +03:00
  • b4c6697703 Added Fmax test project for Gowin Konstantin Pavlov 2022-05-16 18:56:57 +03:00
  • f2ed27297d Added Fmax test projects for Quartus and for Vivado Konstantin Pavlov 2022-05-01 15:03:04 +03:00
  • 8d956479da Added Fmax computation script for Xilinx Vivado Konstantin Pavlov 2022-05-01 14:57:30 +03:00
  • 9ea8e5e037 Done fifo buffer and tests Konstantin Pavlov 2022-05-01 14:52:53 +03:00
  • f74126e5d6 Minor style fixes Konstantin Pavlov 2022-05-01 14:50:23 +03:00
  • fd06088078 Added read ahead buffer Konstantin Pavlov 2022-04-25 03:43:52 +03:00
  • a6aa3c3893 Done fifo initialization Konstantin Pavlov 2022-04-25 01:06:34 +03:00
  • 66ff427e1e Added error suppression for Modelsim script Konstantin Pavlov 2022-04-25 01:03:37 +03:00
  • 98040673a3 Added fifo initialization Konstantin Pavlov 2022-04-23 10:12:04 +03:00
  • 68b33a10d4 Added simple UART logger Konstantin Pavlov 2022-04-19 04:29:15 +03:00
  • c6d4f60bca Updated mem_writer scripts and example output Konstantin Pavlov 2022-04-05 18:39:41 +03:00
  • 322fa85652 Updated test projects to support dev boards Konstantin Pavlov 2022-04-05 18:35:04 +03:00
  • db847e6e7e Added RAM templates Konstantin Pavlov 2022-03-31 20:20:15 +03:00
  • 90a8836c3d Added clogb2 function Konstantin Pavlov 2022-03-31 15:42:11 +03:00
  • e3cba6a4f6 Changed reset mode to asynchronous for soft_latch.sv Konstantin Pavlov 2022-03-31 15:36:38 +03:00