FPGA/basic_verilog
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  • 1a32f07dfc Added optional WIDTH parameter. Made reset signal to be asynchronous Konstantin Pavlov 2022-03-31 15:31:57 +03:00
  • a928a6c326 Updated Vivado test project to v2. Digilent Arty board does supported now Konstantin Pavlov 2022-03-30 19:40:12 +03:00
  • 4c6c8eabb7 Minor fixes for Quartus test project Konstantin Pavlov 2022-03-30 19:28:46 +03:00
  • a2f57048dc Added original DP RAM templates from Quartus and Vivado Konstantin Pavlov 2022-03-15 15:37:09 +03:00
  • 4563fe0f93 Added ascii hex file generator script Konstantin Pavlov 2022-02-20 08:13:37 +03:00
  • c3362fb4a2 Added note on MIF file initialization Konstantin Pavlov 2022-02-20 06:39:03 +03:00
  • 343abf82f7 Added fifo initialization from file Konstantin Pavlov 2022-02-20 05:50:35 +03:00
  • 2fad2973d0 Added utility script Konstantin Pavlov 2022-02-20 05:17:05 +03:00
  • a1608c2326 Added performance variant of encoder and tb Konstantin Pavlov 2021-12-25 22:54:55 +03:00
  • 76674549c3 Added teo types of encoders Konstantin Pavlov 2021-12-25 22:53:30 +03:00
  • fe28e261e6 Added clock jitter Konstantin Pavlov 2021-12-25 22:52:24 +03:00
  • 090372196e Added AXI templates (originally from Vivado component wizard) Konstantin Pavlov 2021-12-24 16:37:13 +03:00
  • 36f89f2554 Rewritten arst conditions in cdc_strobe.sv Konstantin Pavlov 2021-12-15 11:17:10 +03:00
  • b91f6adac5 Added batch update script for your git repos Konstantin Pavlov 2021-11-18 18:38:10 +03:00
  • 937edbeb98 Added recursive build script Konstantin Pavlov 2021-11-09 14:47:29 +03:00
  • 29df4d58b8 Quartus demands to split if conditions Konstantin Pavlov 2021-11-09 05:34:16 +03:00
  • 2499f3a2ea Added Intel HLS scripts and boilerplate Konstantin Pavlov 2021-11-03 17:45:33 +03:00
  • 6c5ef366e7 Added Vivado quick project template Konstantin Pavlov 2021-11-01 14:48:05 +03:00
  • b87a6bfad0 Added testbench template Konstantin Pavlov 2021-11-01 14:47:08 +03:00
  • a80efe16c1 Added more cleaning scripts Konstantin Pavlov 2021-10-28 11:46:38 +03:00
  • 39490aed15 Added typical .gitignore-files for FPGA projects Konstantin Pavlov 2021-10-28 10:03:57 +03:00
  • 9203d17a63 Added cleaning scripts Konstantin Pavlov 2021-10-28 10:02:41 +03:00
  • fdede74311 Added scripts for back-annotate and git-merge Konstantin Pavlov 2021-10-18 09:23:55 +03:00
  • bcc548f914 SImplified reverse_vector.sv code Konstantin Pavlov 2021-09-13 11:17:58 +03:00
  • 0e19b10433 Updated cdc_strobe. Used gray counter under the hood Konstantin Pavlov 2021-09-11 11:04:43 +03:00
  • 261e0565cf Added Vivado initialization code Konstantin Pavlov 2021-08-18 16:31:19 +03:00
  • 871c92454e Added exporting script for Vivado Konstantin Pavlov 2021-08-09 16:19:16 +03:00
  • 0cb8ee915c Updated version autoincrement script for Quartus Konstantin Pavlov 2021-07-29 13:19:29 +03:00
  • 5156db4ebc Added SMA and tb Konstantin Pavlov (ms) 2021-07-29 02:08:53 +03:00
  • 4cd95ad2dc Added universal block RAM fifo Konstantin Pavlov (ms) 2021-07-19 01:45:45 +03:00
  • 1efbd7c243 Added soft_latch module and testbench Konstantin Pavlov 2021-07-09 17:24:20 +03:00
  • d262582ea9
         Update README.md Konstantin Pavlov 2021-07-07 17:39:43 +03:00
  • 2845a2a836 Updated lifo module to support FWFT and normal modes Konstantin Pavlov 2021-07-06 14:15:35 +03:00
  • 452b3574ff Added single clock fifo modules (two variants) Konstantin Pavlov 2021-07-05 09:12:14 +03:00
  • cb224284b1 Added synchronizer modules Konstantin Pavlov 2021-06-11 17:39:06 +03:00
  • d8beb37f01 Added Vivado-specific scripts Konstantin Pavlov 2021-06-03 17:01:55 +03:00
  • 48e9ddef7e Added Modelsim cleaning script Konstantin Pavlov 2021-05-27 12:54:51 +03:00
  • aa52420d17 Updated Quartus Makefile and the reference project Konstantin Pavlov 2021-04-12 12:45:55 +03:00
  • 111dbc65c6 Test project for iterative compilation Quartus projects Konstantin Pavlov 2021-02-05 16:13:27 +03:00
  • 3619810053 Added fast counter sources Konstantin Pavlov 2021-02-05 16:12:05 +03:00
  • c243e1d918 Added Quartus Makefile. Customizable and gives faster compilation Konstantin Pavlov 2021-02-05 16:10:16 +03:00
  • f3075c28a2 Added SV version of UART receiver Konstantin Pavlov 2021-01-27 10:58:54 +03:00
  • 536a8b83d2 Rewriting UART modules to SystemVerilog Konstantin Pavlov 2021-01-26 15:30:56 +03:00
  • b4b191c26f Minor code style update Konstantin Pavlov 2021-01-26 15:24:09 +03:00
  • cf3b4f5d20 Moved all bencmarks to the separate directory Konstantin Pavlov 2021-01-26 15:16:11 +03:00
  • 1b844726dc
         Update README.md Konstantin Pavlov 2020-12-22 11:14:44 +03:00
  • 3760990e5a Added UART-like shifters for for simple synchronous messaging inside the FPGA or between FPGAs Konstantin Pavlov 2020-12-18 16:14:10 +03:00
  • 68922a34d2 Updated benchmark projects. Added 'benchmark_results.txt' that i got on my machine Konstantin Pavlov 2020-12-17 18:42:52 +03:00
  • d44ef08c2c Added benchmark project for Xilinx ISE Design Suite Konstantin Pavlov 2020-12-17 17:58:16 +03:00
  • fee423776f Updates clean script for Quartus projects Konstantin Pavlov 2020-12-15 17:19:48 +03:00
  • 8980f487e9 Added benchmark project for Gowin FPGAs Konstantin Pavlov 2020-12-11 13:49:16 +03:00
  • 303665d784 Added cleaning script for Vivado projects Konstantin Pavlov 2020-11-03 16:54:58 +03:00
  • f5f3d32951 Fixes for delayed_event module Konstantin Pavlov 2020-11-03 11:23:37 +03:00
  • 2d2041a663 Fixed usedw[] calculations in preview_fifo. Other minor fixes Konstantin Pavlov 2020-10-30 11:51:59 +03:00
  • eb69a3a374 Added project archieving for Quartus post-flow script Konstantin Pavlov 2020-10-30 11:48:19 +03:00
  • 002db3191e Added dalayed_event module Konstantin Pavlov 2020-10-30 11:40:27 +03:00
  • 3ddb800544 Updated preview_fifo to support two word writes Konstantin Pavlov 2020-08-09 01:08:56 +03:00
  • aa1ac56e14 Added ALTERA_TAPS delay type Konstantin Pavlov 2020-07-16 16:33:04 +03:00
  • b57c3a9ceb Updated delay module. Added block RAM implementation Konstantin Pavlov 2020-07-09 16:14:28 +03:00
  • d2f436d5dc Added preview FIFO testbench Konstantin Pavlov 2020-07-09 16:09:20 +03:00
  • d07d0ad5f4 Added preview FIFO Konstantin Pavlov 2020-07-09 16:02:57 +03:00
  • bb246b3568 Updated edge_detect to v.3 Konstantin Pavlov 2020-05-22 15:59:50 +03:00
  • ea6833b63e Added DSE launch script Konstantin Pavlov 2020-05-22 14:47:06 +03:00
  • 05fd57f2b8 Added Quartus project cleaning script Konstantin Pavlov 2020-05-22 11:45:23 +03:00
  • c2ec8d320d Added testbench screenshots Konstantin Pavlov 2020-05-06 03:56:30 +03:00
  • e68483d99a Added PDM modulator Konstantin Pavlov 2020-05-06 03:52:20 +03:00
  • 380f3a1f14 Added PWM modulator module and a testbench Konstantin Pavlov 2020-05-05 06:52:51 +03:00
  • d5030cfb5d Updated pulse_gen to ver.2 Konstantin Pavlov 2020-05-05 06:51:23 +03:00
  • eba4111ce1 Added JTAG server setup script Konstantin Pavlov 2020-04-23 18:03:21 +03:00
  • ec0bdd4948 Minor fixes Konstantin Pavlov 2020-04-16 10:57:36 +03:00
  • 4da5e8bc96 Updated readme Konstantin Pavlov 2020-04-07 22:33:24 +03:00
  • d82a3bc050 Merge branch 'master' of https://github.com/pConst/basic_verilog Konstantin Pavlov 2020-04-07 15:36:51 +03:00
  • 8d3ea380a9 added script to set project directory in Vivado Konstantin Pavlov 2020-04-07 14:30:32 +03:00
  • 573cc6e6b8 Added benchmark project for Vivado IDE Konstantin Pavlov 2020-04-07 14:29:25 +03:00
  • 1840a5a8ca Updated post flow script for Vivado Konstantin Pavlov 2020-04-07 14:14:19 +03:00
  • ff356f13e0 Two random generators with different seed values Konstantin Pavlov 2020-02-28 17:55:54 +03:00
  • 8db4b773b9 Added test project template Konstantin Pavlov 2020-02-27 20:40:08 +03:00
  • f1604e8736 Added gray code converters Konstantin Pavlov 2020-02-25 15:38:56 +03:00
  • b8064ecef9 Fixed header info in some testbenches Konstantin Pavlov 2020-02-25 15:38:02 +03:00
  • c189b88688 Added PRBS test sequence generator and chekker Konstantin Pavlov 2020-02-11 15:34:00 +03:00
  • 8fa82449ed Added more scripts for Quartus IDE Konstantin Pavlov 2020-02-07 02:35:04 +03:00
  • 4150134587 Added pulse generator module Konstantin Pavlov 2020-02-07 02:28:00 +03:00
  • 4682b7e4d5 Added adder_tree module and testbench Konstantin Pavlov 2019-12-13 13:26:07 +03:00
  • 8936cd36e6 Updated delay module to support LENGTH=0 Konstantin Pavlov 2019-12-13 13:23:54 +03:00
  • 21f4580a78 Updated SR trigger variation modules Konstantin Pavlov 2019-12-13 13:19:49 +03:00
  • 51f484b204 Restored testbenches Konstantin Pavlov 2019-11-15 15:35:41 +03:00
  • 7c9acbfbf0 Added pulse_stretch.sv and testbench Konstantin Pavlov 2019-11-15 15:32:26 +03:00
  • 99eaebc08a Deleted obsolete files Konstantin Pavlov 2019-11-14 12:26:14 +03:00
  • 7dec15cfe5 Added pulse_stretch.sv module Konstantin Pavlov 2019-11-14 12:22:18 +03:00
  • 0f33c1da67 Added module to convert data from big-endian to little-endian and back Konstantin Pavlov 2019-10-17 10:48:49 +03:00
  • 7bd8c659f3 Added module to pack Verilog-2001 arrays Konstantin Pavlov 2019-10-17 10:47:51 +03:00
  • 6b99e1fdab Added script to program Altera/Intel devices Konstantin Pavlov 2019-10-02 13:40:27 +03:00
  • 928bced8b1 Added iverilog-gtlwave simulation script for Windows Konstantin Pavlov 2019-09-30 01:33:19 +03:00
  • a733fc5382 Added leave_one_hot module Konstantin Pavlov 2019-07-28 14:08:17 +03:00
  • 7f1454e6f7 Updated TCL scripts Konstantin Pavlov 2019-07-28 12:26:13 +03:00
  • c77026f2bf Removed obsolete files Konstantin Pavlov 2019-06-28 03:23:04 +03:00
  • 066fd2f5dc Added Vivado post-flow script boilerplate Konstantin Pavlov 2019-06-28 03:18:13 +03:00
  • 306259c45f Added module to switch dims in a 2D systemverilog array Konstantin Pavlov 2019-06-28 01:31:19 +03:00
  • 3474f7b505 Updated dynamic_delay to allow delays bit-wize, not just element-wize Konstantin Pavlov 2019-05-26 21:12:19 +03:00
  • 431d06145b Added SIMULATION define to the testbench template Konstantin Pavlov 2019-05-24 14:23:19 +03:00