FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-28 07:02:55 +08:00
Code Issues Releases Wiki Activity

Commit Graph

  • 5a05b4df56 Added helper script to launch and initialize system console Konstantin Pavlov 2019-05-24 14:16:41 +03:00
  • 6e6b4905c5 Renaming scripts Konstantin Pavlov 2019-05-24 14:14:43 +03:00
  • 7399deb17d Added Avalon master templates Konstantin Pavlov 2019-05-24 14:03:34 +03:00
  • 5bde0a502e Added version generating script to example project Konstantin Pavlov 2019-04-16 04:46:38 +03:00
  • cd16cc5f9c Auto-incrementing project version for Quartus IDE Konstantin Pavlov 2019-04-16 04:45:23 +03:00
  • 51951d842d Added classic TAN timing analizer report parsing Konstantin Pavlov 2019-04-16 04:44:25 +03:00
  • 6bdafa6d56 Added errors supression script for Vivado to allow 'proto' projects w/o pin assignments Konstantin Pavlov 2019-04-16 04:42:39 +03:00
  • 1fdc31ad05 Added quartus benchmarking project Konstantin Pavlov 2019-04-15 02:37:45 +03:00
  • 8c420a1570 Updated reporting script to write total ompilation time Konstantin Pavlov 2019-04-14 11:03:16 +03:00
  • 57de1109bc Selector width fixed in dynamic_delay.sv Konstantin Pavlov 2019-04-14 00:07:00 +03:00
  • b6028753ef Minor tcl script fixes Konstantin Pavlov 2019-03-30 18:16:28 +03:00
  • 80bcda370b Added a bunch of TCL scripts Konstantin Pavlov 2019-02-17 23:48:21 +03:00
  • bea7cad324 Added quick shortcut for Modelsim compilation Konstantin Pavlov 2019-03-11 00:10:07 +03:00
  • fe43d58156 Drastically simplyfied universal SPI master Konstantin Pavlov 2019-03-11 00:08:56 +03:00
  • fbb6ecff17 Added System Console initialization script Konstantin Pavlov 2019-03-10 21:05:01 +03:00
  • 732a6883d5 Added scripts directory. Added SOF to RBF converter Konstantin Pavlov 2019-03-10 20:35:09 +03:00
  • 0b8a793478 Fixed delay length Konstantin Pavlov 2019-02-27 15:08:26 +03:00
  • 2713e374c1 Lots of minor edits Konstantin Pavlov 2019-02-23 00:20:06 +03:00
  • f04430c7a8 Added universal spi master module Konstantin Pavlov 2019-02-17 22:13:26 +03:00
  • f8794b5c48 Added Modelsim compile TCL script Konstantin Pavlov (fm) 2019-02-11 11:39:06 +03:00
  • 9c1670a472 Added sample asynchronous external device logic Konstantin Pavlov (fm) 2019-02-08 13:56:50 +03:00
  • 8e61fc2036 Added initialization for testbench clocks and resets Konstantin Pavlov (fm) 2019-01-29 13:24:06 +03:00
  • cb280f51cf Fixed RS triggers declaration syntax Konstantin Pavlov (fm) 2019-01-09 15:12:55 +03:00
  • ba53bc5486 Updated SystemVerilog variants of delay modules Konstantin Pavlov (fm) 2019-01-09 14:59:39 +03:00
  • a6280adfde Added SystemVerilog version of clock divider Konstantin Pavlov (fm) 2019-01-09 14:38:52 +03:00
  • d971d108cf Removed obsolete delay modules Konstantin Pavlov (fm) 2019-01-09 14:34:45 +03:00
  • a66013eb1c Removed obsolete RS trigger modules Konstantin Pavlov (fm) 2019-01-09 14:33:13 +03:00
  • 2d8e67db35 snake_case for reverse_vector module and its testbench Konstantin Pavlov (fm) 2019-01-09 14:32:02 +03:00
  • 842496f0da Updated SystemVerilog variants of SR trigger featuring dominant logic state Konstantin Pavlov (fm) 2019-01-09 14:28:29 +03:00
  • d39ccb2dd7 Added paramater to instantiation template of delay.sv Konstantin Pavlov (fm) 2019-01-09 14:23:45 +03:00
  • 807cc4303d Added .ena input to delay.sv Konstantin Pavlov (fm) 2019-01-09 13:58:20 +03:00
  • 6d933d2ea2 snake_case naming for clock divider and main testbench template Konstantin Pavlov (fm) 2018-12-11 15:42:09 +03:00
  • 6ec509c3c6 snake_case naming for edge detector Konstantin Pavlov (fm) 2018-12-11 15:34:14 +03:00
  • 6b22c900b1 Updated EdgeDetect module instantiation Konstantin Pavlov (fm) 2018-12-07 11:26:03 +03:00
  • 24312652ab Combinational implementation of EdgeDetector with zero latency Konstantin Pavlov (fm) 2018-12-04 12:33:26 +03:00
  • 5e8c4c2ced Minor fixes and comments Konstantin Pavlov 2018-09-16 17:26:39 +03:00
  • 699c489592 Added bin2pos and pos2bin combinational modules Konstantin Pavlov 2018-09-16 15:41:21 +03:00
  • ca43500c00 Added ReverseVector combinational module Konstantin Pavlov 2018-09-16 01:20:23 +03:00
  • b7f3bee0fd Added SystemVerilog variant of main_tb Konstantin Pavlov 2018-08-01 07:02:29 +03:00
  • f838698dda Removed tabs Konstantin Pavlov 2018-08-01 07:00:37 +03:00
  • 829d84b4c7 Added element counter initialization Konstantin Pavlov 2018-08-01 06:39:08 +03:00
  • 2282e26c1f Added single-clock FIFO and LIFO buffer modules Konstantin Pavlov 2018-07-29 08:23:20 +03:00
  • fc47ffdcb7 Added SystemVerilog variants of clock divider and edge detector Konstantin Pavlov 2018-07-29 08:14:23 +03:00
  • 7bda757047 Added integer division module Konstantin Pavlov (pt) 2016-12-14 12:51:46 +03:00
  • e1701818a5 Added ActionBurst2. Minor fix to ActionBurst Konstantin Pavlov (pt) 2016-12-13 15:11:03 +03:00
  • 0000b487e1 Uniform instantiation templates. Synch() renamed to StaticDelay() Konstantin Pavlov (pt) 2016-12-12 11:41:56 +03:00
  • f871b7c369 Returned back some condition checks in UartTxExtreme Konstantin Pavlov (pt) 2016-05-20 15:57:31 +03:00
  • 392bc24c8e UartExtreme rewrite and simulation done Konstantin Pavlov (pt) 2016-04-10 16:13:09 +03:00
  • a045839afd Added extreme minimal UART implementations. Testing in progress Konstantin Pavlov (pt) 2016-04-07 13:42:47 +03:00
  • 1de6441c14 Minor fixes Konstantin Pavlov (pt) 2016-04-01 03:34:05 +03:00
  • ee9d1b9e66 Added UART receiver and transmitter modules Konstantin Pavlov (pt) 2016-03-30 21:33:41 +03:00
  • 9e19abc733 Added Xilinx Picoblaze and its Altera version Pacoblaze as a great HDL programming examples Konstantin Pavlov (pt) 2016-03-24 21:10:37 +03:00
  • c31bb14628 ActionBurst module and minor fixes Konstantin Pavlov (pt) 2016-03-23 21:18:08 +03:00
  • 2a3f609428 "Enable" input in DeBounce module Konstantin Pavlov (en) 2016-01-19 19:23:27 +03:00
  • e5aed02305 Added StaticDelay. Updated Main_tb Konstantin Pavlov (en) 2016-01-15 19:25:06 +03:00
  • d3f999e07e Explicit nrst naming for better Quartus compatibility Konstantin Pavlov (pt) 2016-01-07 14:05:06 +03:00
  • 78403cdec0 Added instantiation templates and testbenches for selected modules Konstantin Pavlov (pt) 2016-01-01 22:39:14 +03:00
  • c1b04ecd87 Fixed error in Synch module Konstantin Pavlov (pt) 2015-12-25 23:20:33 +03:00
  • 4a5b91219e Added pulse generator modules Konstantin Pavlov (pt) 2015-12-24 19:05:06 +03:00
  • df4a0b222c Added testbench template Konstantin Pavlov (pt) 2015-12-18 00:28:22 +03:00
  • 40533743d7 Added altera cookbook Konstantin Pavlov (pt) 2015-12-15 22:44:58 +03:00
  • 25b74793e0 Initial commit Konstantin Pavlov (pt) 2015-12-14 21:13:15 +03:00