# TCL File Generated by Component Editor 8.0 # Sat May 31 20:41:17 PDT 2008 # DO NOT MODIFY # +----------------------------------- # | module burst_read_master # | set_module_property DESCRIPTION "Custom Avalon-MM Masters" set_module_property NAME master_template set_module_property VERSION 1.0 set_module_property GROUP "Templates" set_module_property AUTHOR JCJB set_module_property ICON_PATH ALTERA_LOGO_ANIM.gif set_module_property DISPLAY_NAME master_template set_module_property TOP_LEVEL_HDL_FILE custom_master.v set_module_property TOP_LEVEL_HDL_MODULE custom_master set_module_property INSTANTIATE_IN_SYSTEM_MODULE true set_module_property EDITABLE false set_module_property SIMULATION_MODEL_IN_VERILOG false set_module_property SIMULATION_MODEL_IN_VHDL false set_module_property SIMULATION_MODEL_HAS_TULIPS false set_module_property SIMULATION_MODEL_IS_OBFUSCATED false # | # +----------------------------------- set_module_property ELABORATION_CALLBACK elaborate_me set_module_property VALIDATION_CALLBACK validate_me # +----------------------------------- # | files # | add_file custom_master.v {SYNTHESIS SIMULATION} add_file burst_write_master.v {SYNTHESIS SIMULATION} add_file burst_read_master.v {SYNTHESIS SIMULATION} add_file write_master.v {SYNTHESIS SIMULATION} add_file latency_aware_read_master.v {SYNTHESIS SIMULATION} # | # +----------------------------------- # +----------------------------------- # | parameters # | # Avalon Master Settings add_parameter MASTER_DIRECTION Integer 0 "Sets the master direction between read (0) and write (1) transfers" set_parameter_property MASTER_DIRECTION VISIBLE true set_parameter_property MASTER_DIRECTION DISPLAY_NAME "Master Direction" set_parameter_property MASTER_DIRECTION GROUP "Avalon-MM Master Properties" set_parameter_property MASTER_DIRECTION AFFECTS_PORT_WIDTHS true set_parameter_property MASTER_DIRECTION ALLOWED_RANGES {"0:Read" "1:Write"} add_parameter DATA_WIDTH Integer 32 "Width of the data path" set_parameter_property DATA_WIDTH VISIBLE true set_parameter_property DATA_WIDTH DISPLAY_NAME "Data Width" set_parameter_property DATA_WIDTH GROUP "Avalon-MM Master Properties" set_parameter_property DATA_WIDTH AFFECTS_PORT_WIDTHS true set_parameter_property DATA_WIDTH ALLOWED_RANGES {8 16 32 64 128 256 512 1024} add_parameter ADDRESS_WIDTH Integer "32" "Address Width" set_parameter_property ADDRESS_WIDTH VISIBLE true set_parameter_property ADDRESS_WIDTH DISPLAY_NAME "Address Width" set_parameter_property ADDRESS_WIDTH GROUP "Avalon-MM Master Properties" set_parameter_property ADDRESS_WIDTH AFFECTS_PORT_WIDTHS true set_parameter_property ADDRESS_WIDTH ALLOWED_RANGES {32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 14 13 12 11 10 9 8 7 6 5 4} # Burst Settings add_parameter BURST_CAPABLE Integer 0 "Enable bursting" set_parameter_property BURST_CAPABLE VISIBLE true set_parameter_property BURST_CAPABLE DISPLAY_NAME "Burst Capable" set_parameter_property BURST_CAPABLE GROUP "Burst Properties" set_parameter_property BURST_CAPABLE AFFECTS_PORT_WIDTHS true set_parameter_property BURST_CAPABLE ALLOWED_RANGES {"0:Disabled" "1:Enabled"} add_parameter MAXIMUM_BURST_COUNT Integer "2" "Maximum Burst Count" set_parameter_property MAXIMUM_BURST_COUNT VISIBLE true set_parameter_property MAXIMUM_BURST_COUNT DISPLAY_NAME "Maximum Burst Count" set_parameter_property MAXIMUM_BURST_COUNT GROUP "Burst Properties" set_parameter_property MAXIMUM_BURST_COUNT AFFECTS_PORT_WIDTHS false set_parameter_property MAXIMUM_BURST_COUNT ALLOWED_RANGES {1 2 4 8 16 32 64 128} add_parameter BURST_COUNT_WIDTH Integer "2" "Enable bursting" set_parameter_property BURST_COUNT_WIDTH VISIBLE false set_parameter_property BURST_COUNT_WIDTH DISPLAY_NAME "Burst Count Width" set_parameter_property BURST_COUNT_WIDTH GROUP "Burst Properties" set_parameter_property BURST_COUNT_WIDTH AFFECTS_PORT_WIDTHS true set_parameter_property BURST_COUNT_WIDTH ALLOWED_RANGES {1:8} # Other Settings add_parameter FIFO_DEPTH Integer "32" "FIFO depth" set_parameter_property FIFO_DEPTH VISIBLE true set_parameter_property FIFO_DEPTH DISPLAY_NAME "FIFO Depth" set_parameter_property FIFO_DEPTH GROUP "Other Properties" set_parameter_property FIFO_DEPTH AFFECTS_PORT_WIDTHS false set_parameter_property FIFO_DEPTH ALLOWED_RANGES {4 8 16 32 64 128 256} add_parameter FIFO_DEPTH_LOG2 Integer "5" "log2(FIFO Depth)" set_parameter_property FIFO_DEPTH_LOG2 VISIBLE false set_parameter_property FIFO_DEPTH_LOG2 DISPLAY_NAME "log2(FIFO Depth)" set_parameter_property FIFO_DEPTH_LOG2 GROUP "Other Properties" set_parameter_property FIFO_DEPTH_LOG2 AFFECTS_PORT_WIDTHS false set_parameter_property FIFO_DEPTH_LOG2 ALLOWED_RANGES {2:8} add_parameter MEMORY_BASED_FIFO Integer 1 "Select false if you want register based (0) FIFO instead of memory (1)" set_parameter_property MEMORY_BASED_FIFO VISIBLE true set_parameter_property MEMORY_BASED_FIFO DISPLAY_NAME "Memory based FIFO" set_parameter_property MEMORY_BASED_FIFO GROUP "Other Properties" set_parameter_property MEMORY_BASED_FIFO AFFECTS_PORT_WIDTHS false set_parameter_property MEMORY_BASED_FIFO ALLOWED_RANGES {"1:Memory" "0:Logic"} # | # +----------------------------------- # +----------------------------------- # | connection point clock_reset # | add_interface clock_reset clock end set_interface_property clock_reset ptfSchematicName "" add_interface_port clock_reset clk clk Input 1 add_interface_port clock_reset reset reset Input 1 # | # +----------------------------------- # +----------------------------------- # | connection point avalon_master # | add_interface avalon_master avalon start set_interface_property avalon_master linewrapBursts false set_interface_property avalon_master adaptsTo "" set_interface_property avalon_master doStreamReads false set_interface_property avalon_master doStreamWrites false set_interface_property avalon_master burstOnBurstBoundariesOnly false set_interface_property avalon_master ASSOCIATED_CLOCK clock_reset add_interface_port avalon_master master_address address Output -1 add_interface_port avalon_master master_read read Output 1 add_interface_port avalon_master master_write write Output 1 add_interface_port avalon_master master_byteenable byteenable Output -1 add_interface_port avalon_master master_readdata readdata Input -1 add_interface_port avalon_master master_readdatavalid readdatavalid Input 1 add_interface_port avalon_master master_writedata writedata Output -1 add_interface_port avalon_master master_burstcount burstcount Output -1 add_interface_port avalon_master master_waitrequest waitrequest Input 1 # | # +----------------------------------- # +----------------------------------- # | connection point control # | add_interface control conduit end set_interface_property control ASSOCIATED_CLOCK clock_reset add_interface_port control control_fixed_location export Input 1 add_interface_port control control_read_base export Input -1 add_interface_port control control_write_base export Input -1 add_interface_port control control_read_length export Input -1 add_interface_port control control_write_length export Input -1 add_interface_port control control_go export Input 1 add_interface_port control control_done export Output 1 add_interface_port control control_early_done export Output 1 # | # +----------------------------------- # +----------------------------------- # | connection point user # | add_interface user conduit end set_interface_property user ASSOCIATED_CLOCK clock_reset add_interface_port user user_read_buffer export Input 1 add_interface_port user user_buffer_output_data export Output -1 add_interface_port user user_data_available export Output 1 add_interface_port user user_write_buffer export Input 1 add_interface_port user user_buffer_input_data export Input -1 add_interface_port user user_buffer_full export Output 1 # | # +----------------------------------- proc elaborate_me {} { # set all the new port widths set the_data_width [get_parameter_value DATA_WIDTH] set the_byteenable_width [expr {$the_data_width / 8} ] set the_address_width [get_parameter_value ADDRESS_WIDTH] set the_burst_count_width [get_parameter_value BURST_COUNT_WIDTH] set_port_property control_read_base WIDTH $the_address_width set_port_property control_read_length WIDTH $the_address_width set_port_property control_write_base WIDTH $the_address_width set_port_property control_write_length WIDTH $the_address_width set_port_property user_buffer_input_data WIDTH $the_data_width set_port_property user_buffer_output_data WIDTH $the_data_width set_port_property master_address WIDTH $the_address_width set_port_property master_byteenable WIDTH $the_byteenable_width set_port_property master_readdata WIDTH $the_data_width set_port_property master_writedata WIDTH $the_data_width set_port_property master_burstcount WIDTH $the_burst_count_width # determine the master direction and burst capabilities set the_master_direction [get_parameter_value MASTER_DIRECTION] set the_burst_capable [get_parameter_value BURST_CAPABLE] # switch between read and write master signals (excluding burstcount) if { $the_master_direction == 0 } { set_port_property control_read_base TERMINATION false set_port_property control_read_length TERMINATION false set_port_property control_write_base TERMINATION true set_port_property control_write_length TERMINATION true set_port_property control_early_done TERMINATION false set_port_property user_read_buffer TERMINATION false set_port_property user_write_buffer TERMINATION true set_port_property user_buffer_input_data TERMINATION true set_port_property user_buffer_output_data TERMINATION false set_port_property user_data_available TERMINATION false set_port_property user_buffer_full TERMINATION true set_port_property master_read TERMINATION false set_port_property master_write TERMINATION true set_port_property master_readdata TERMINATION false set_port_property master_readdatavalid TERMINATION false set_port_property master_writedata TERMINATION true } else { set_port_property control_read_base TERMINATION true set_port_property control_read_length TERMINATION true set_port_property control_write_base TERMINATION false set_port_property control_write_length TERMINATION false set_port_property control_early_done TERMINATION true set_port_property user_read_buffer TERMINATION true set_port_property user_write_buffer TERMINATION false set_port_property user_buffer_input_data TERMINATION false set_port_property user_buffer_output_data TERMINATION true set_port_property user_data_available TERMINATION true set_port_property user_buffer_full TERMINATION false set_port_property master_read TERMINATION true set_port_property master_write TERMINATION false set_port_property master_readdata TERMINATION true set_port_property master_readdatavalid TERMINATION true set_port_property master_writedata TERMINATION false } # enable/disable the burstcount signal if { $the_burst_capable == 0 } { set_port_property master_burstcount TERMINATION true } else { set_port_property master_burstcount TERMINATION false } } proc validate_me {} { # read in all the parameter that matter for validation set the_burst_capable [get_parameter_value BURST_CAPABLE] set the_maximum_burst_count [get_parameter_value MAXIMUM_BURST_COUNT] set the_fifo_depth [get_parameter_value FIFO_DEPTH] # when burst is enabled check to make sure FIFO depth is at least twice as large (also enable/disable burst count) if { $the_burst_capable == 1 } { set_parameter_property MAXIMUM_BURST_COUNT ENABLED true if { $the_fifo_depth < [expr {$the_maximum_burst_count * 2}] } { send_message Error "The FIFO Depth must be at least twice as large as Maximum Burst Count." } } else { set_parameter_property MAXIMUM_BURST_COUNT ENABLED false } set the_burst_count [get_parameter_value MAXIMUM_BURST_COUNT] set the_burst_count_width [expr {(log($the_burst_count) / log(2)) + 1}] set the_fifo_depth [get_parameter_value FIFO_DEPTH] set the_fifo_depth_log2 [expr {log($the_fifo_depth) / log(2)}] set_parameter_value BURST_COUNT_WIDTH $the_burst_count_width set_parameter_value FIFO_DEPTH_LOG2 $the_fifo_depth_log2 }