#------------------------------------------------------------------------------
# .gitignore for Mentor Modelsim
# published as part of https://github.com/pConst/basic_verilog
# Konstantin Pavlov, pavlovconst@gmail.com
#------------------------------------------------------------------------------

# INFO ------------------------------------------------------------------------
# rename the file to ".gitignore" and place into your testbench directory
#


transcript
work*
modelsim.ini
start_time.txt
vsim.wlf
vish_stacktrace.vstf