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// baeckler - 05-05-2006
// testbench for min_max

////////////////////////////////////////////

module min_max_tb ();

parameter WIDTH = 8;

reg clk,rst,sign;
reg [WIDTH-1:0] a,b;
wire [WIDTH-1:0] min_ab,max_ab;
wire [WIDTH-1:0] min_abu,max_abu;
wire [WIDTH-1:0] min_ab8,max_ab8;

min_max_signed mm (.clk(clk),.rst(rst),.a(a),.b(b),
	.min_ab(min_ab),.max_ab(max_ab));
	defparam mm .WIDTH = WIDTH;

min_max_unsigned mmu (.clk(clk),.rst(rst),.a(a),.b(b),
	.min_ab(min_abu),.max_ab(max_abu));
	defparam mmu .WIDTH = WIDTH;

min_max_8bit m8 (.clk(clk),.rst(rst),.a_in(a),.b_in(b),
	.is_signed(sign),
	.min_ab(min_ab8),.max_ab(max_ab8));

reg fail = 0;
initial begin
	clk = 0;
	rst = 0;
	sign = 0;
	#10 rst = 1;
	#10 rst = 0;
	#1000000 if (!fail) $display ("PASS");
	$stop();
end

always begin
	#100 clk = ~clk;
end

always @(negedge clk) begin
	a = $random;
	b = $random;
	sign = $random;
end

always @(posedge clk) begin
	#10 if (sign & (min_ab8 != min_ab || min_ab8 != min_ab) |
			!sign & (min_ab8 != min_abu || min_ab8 != min_abu))
		begin
			$display ("Mismatch at time %d",$time);
			fail = 1;
		end
end


endmodule