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99 lines
3.0 KiB
Verilog
99 lines
3.0 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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//baeckler - 02-13-2007
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module arbiter_tb ();
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reg [15:0] req;
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reg [3:0] base;
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wire [15:0] grant, grant_two;
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reg fail;
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// weaker unit for testing
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reference_arbiter arb (.req(req),.base(base),.grant(grant));
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// convert the encoded base to one hot
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// ideally it would be generated in one hot
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reg [15:0] decoded_base;
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always @(*) begin
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decoded_base = 0;
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decoded_base[base] = 1'b1;
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end
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// device under test
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arbiter a2 (.req(req),.grant(grant_two),.base(decoded_base));
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defparam a2 .WIDTH = 16;
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always begin
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#100
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req = $random & $random & $random;
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base = $random;
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#5
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if (grant !== grant_two) begin
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$display ("Mismatch at time %d",$time);
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fail = 1;
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end
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end
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initial begin
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fail = 0;
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#1000000 if (!fail) $display ("PASS");
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$stop();
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end
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endmodule
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/////////////////////////////////////////
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// Less efficient easier to understand
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// unit for reference
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/////////////////////////////////////////
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module reference_arbiter (
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req,grant,base
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);
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input [15:0] req;
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output [15:0] grant;
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input [3:0] base;
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// rotate the request lines
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wire [15:0] b0 = base[0] ? {req[0],req[15:1]} : req[15:0] ;
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wire [15:0] b1 = base[1] ? {b0[1:0],b0[15:2]} : b0[15:0] ;
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wire [15:0] b2 = base[2] ? {b1[3:0],b1[15:4]} : b1[15:0] ;
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wire [15:0] b3 = base[3] ? {b2[7:0],b2[15:8]} : b2[15:0] ;
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// pick the lowest one for a grant
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wire [15:0] rotated_grant = b3 & ~(b3-1);
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// unrotate the grant
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wire [15:0] b4 = base[0] ? {rotated_grant[14:0],rotated_grant[15]} : rotated_grant[15:0] ;
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wire [15:0] b5 = base[1] ? {b4[13:0],b4[15:14]} : b4[15:0] ;
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wire [15:0] b6 = base[2] ? {b5[11:0],b5[15:12]} : b5[15:0] ;
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wire [15:0] b7 = base[3] ? {b6[7:0],b6[15:8]} : b6[15:0] ;
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assign grant = b7;
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endmodule |