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62 lines
2.4 KiB
Verilog
62 lines
2.4 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 2-13-2006
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// compute sum of 36 bit lines
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//
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// uses nine 6:3 compressors = 27 six-luts
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// plus a 5 bit carry propagate output adder (one bit falls through)
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module thirtysix_six_comp (data,sum);
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input [35:0] data;
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output [5:0] sum;
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wire [5:0] sum;
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wire [5:0] word_l;
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wire [5:0] word_m;
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wire [5:0] word_h;
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wire [2:0] sa,sb,sc,sd,se,sf;
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wire [2:0] slo,sme,shi;
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six_three_comp a (.data(data[5:0]),.sum(sa));
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six_three_comp b (.data(data[11:6]),.sum(sb));
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six_three_comp c (.data(data[17:12]),.sum(sc));
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six_three_comp d (.data(data[23:18]),.sum(sd));
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six_three_comp e (.data(data[29:24]),.sum(se));
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six_three_comp f (.data(data[35:30]),.sum(sf));
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six_three_comp lo (.data({sa[0],sb[0],sc[0],sd[0],se[0],sf[0]}),.sum(slo));
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six_three_comp me (.data({sa[1],sb[1],sc[1],sd[1],se[1],sf[1]}),.sum(sme));
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six_three_comp hi (.data({sa[2],sb[2],sc[2],sd[2],se[2],sf[2]}),.sum(shi));
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wire [7:0] tmp_sum;
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ternary_add t (.a({3'b0,slo}),
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.b({2'b0,sme,1'b0}),
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.c({1'b0,shi,2'b0}),
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.o(tmp_sum));
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defparam t .WIDTH = 6;
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assign sum = tmp_sum[5:0];
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endmodule
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