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88 lines
3.2 KiB
Verilog
88 lines
3.2 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 05-13-2005
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//
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// Efficient implementation of
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// (bus_a == bus_b) || (bus_a == ~bus_b);
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//
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// for Stratix II hardware. Use optimization technique = speed
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//
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module match_or_inv (bus_a,bus_b,match_or_inv);
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parameter WIDTH = 32;
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localparam GROUPS_OF_THREE = WIDTH/3;
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input [WIDTH-1:0] bus_a;
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input [WIDTH-1:0] bus_b;
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output match_or_inv;
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wire [GROUPS_OF_THREE - 1 : 0] groups /* synthesis keep */;
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wire [GROUPS_OF_THREE + WIDTH-(3*GROUPS_OF_THREE) - 1 : 0] reduced_a;
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wire [GROUPS_OF_THREE + WIDTH-(3*GROUPS_OF_THREE) - 1 : 0] reduced_b;
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wire reduced_result;
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genvar i;
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generate
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// simplify each block of 3 vs 3 bus bits into a six LUT and a 1 bit problem
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for (i=0; i<GROUPS_OF_THREE; i=i+1)
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begin : triples
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wire [2:0] part_a;
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wire [2:0] part_b;
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wire m_or_i;
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assign part_a = bus_a[i*3+2:i*3];
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assign part_b = bus_b[i*3+2:i*3];
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assign groups[i] = (part_a == part_b || part_a == ~part_b);
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assign reduced_a[i] = bus_a[i*3];
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assign reduced_b[i] = bus_b[i*3];
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end
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// take care of bus bits when the width isn't a multiple of 3
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for (i=0; i<WIDTH-(3*GROUPS_OF_THREE); i=i+1)
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begin : residue
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assign reduced_a[GROUPS_OF_THREE + i] = bus_a[3*GROUPS_OF_THREE + i];
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assign reduced_b[GROUPS_OF_THREE + i] = bus_b[3*GROUPS_OF_THREE + i];
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end
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endgenerate
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// if the remaining problem is big enough tackle it recursively
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// otherwise just build the gates
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generate
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if ((GROUPS_OF_THREE + WIDTH-(3*GROUPS_OF_THREE)) > 3)
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begin
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match_or_inv helper (.bus_a(reduced_a),.bus_b(reduced_b),.match_or_inv(reduced_result));
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defparam helper .WIDTH = (GROUPS_OF_THREE + WIDTH-(3*GROUPS_OF_THREE));
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end
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else
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begin
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assign reduced_result = (reduced_a == reduced_b || reduced_a == ~reduced_b);
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end
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endgenerate
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// Final answer is the & of all 3 input results and the sub problem result
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assign match_or_inv = (& groups) && reduced_result;
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endmodule |