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72 lines
2.1 KiB
Verilog
72 lines
2.1 KiB
Verilog
// Copyright 2008 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module system_timer_tb ();
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reg clk = 0, rst = 0;
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wire usecond_pulse;
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wire msecond_pulse;
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wire second_pulse;
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wire [9:0] usecond_cntr;
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wire [9:0] msecond_cntr;
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wire [5:0] second_cntr;
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wire [5:0] minute_cntr;
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wire [4:0] hour_cntr;
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wire [9:0] day_cntr;
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system_timer dut (
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.clk,
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.rst,
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.usecond_cntr,
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.msecond_cntr,
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.second_cntr,
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.minute_cntr,
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.hour_cntr,
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.day_cntr,
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.usecond_pulse,
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.msecond_pulse,
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.second_pulse
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);
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defparam dut .CLOCK_MHZ = 100;
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always begin
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#5 clk = ~clk;
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end
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initial begin
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@(negedge clk);
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rst = 1;
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@(negedge clk);
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rst = 0;
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#10000100
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// cursory activity check, better tested in hardware
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if (usecond_cntr == 10'h0 &&
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msecond_cntr == 10'ha) $display ("PASS");
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$stop();
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end
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endmodule |