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55 lines
1.9 KiB
Verilog
55 lines
1.9 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module bin_to_dec_tb ();
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reg [31:0] ins;
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reg [31:0] ins_copy;
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reg [39:0] expected;
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wire [39:0] out;
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reg fail = 0;
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integer n;
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bin_to_dec bd (.ins(ins),.out(out));
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always begin
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#10 ins = $random;
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#1 ins_copy = ins;
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expected = 0;
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for (n=0; n<10; n=n+1)
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begin : chk
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#1 expected = {expected[3:0],expected[39:4]} | (ins_copy % 10);
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ins_copy = ins_copy / 10;
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end
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expected = {expected[3:0],expected[39:4]};
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#1 if (out !== expected) fail = 1;
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end
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initial begin
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#200000 if (!fail) $display ("PASS");
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$stop();
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end
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endmodule
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