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96 lines
3.0 KiB
Verilog
96 lines
3.0 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 05-05-2006
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//
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// This is a trick to generate case statements / LUT masks
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// from an existing comb circuit. It's handy when the structure
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// of the current implementation is getting in the way.
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//
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module make_case_tb ();
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`include "log2.inc"
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localparam IN_WIDTH = 4;
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localparam OUT_WIDTH = 8;
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localparam LOG_OUT_WIDTH = log2(OUT_WIDTH-1);
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reg [IN_WIDTH-1:0] in;
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wire [OUT_WIDTH-1:0] out;
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///////////////////////
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// target function
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///////////////////////
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// drive all inputs from IN
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// merge all outputs to OUT.
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bin_to_asc_hex ba (.in(in),.out(out));
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defparam ba .WIDTH=IN_WIDTH;
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///////////////////////
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// sim loop
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///////////////////////
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integer n,k;
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reg [(1<<IN_WIDTH)-1:0] tmp_mask;
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reg [LOG_OUT_WIDTH-1:0] tmp_out;
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wire [IN_WIDTH-1:0] max_mask = (1<<IN_WIDTH)-1;
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initial begin
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////////////////////////////////////////
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// make a case statement
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////////////////////////////////////////
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$display ("// case statement version");
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$display ("case (in)");
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for (n=0; n<(1<<IN_WIDTH); n=n+1)
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begin
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in = n;
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#5
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$display (" %d'h%x : out = %d'b%b;",
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IN_WIDTH,in,OUT_WIDTH,out);
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end
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$display ("endcase\n");
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////////////////////////////////////////
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// make a look up table for each output
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////////////////////////////////////////
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$display ("// look up table version");
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for (k=0; k<OUT_WIDTH; k=k+1)
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begin
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tmp_mask = 0;
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tmp_out = k;
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for (n=0; n<(1<<IN_WIDTH); n=n+1)
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begin
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in = n;
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#5
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if (out[k]) tmp_mask[n] = 1'b1;
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end
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$display ("wire [%d:0] mask%d = %d'h%x;",
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max_mask,tmp_out,{1'b0,max_mask}+1'b1,tmp_mask);
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$display ("assign out[%d] = mask%d[in];",tmp_out,tmp_out);
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end
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$stop();
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end
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endmodule
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