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93 lines
2.7 KiB
Systemverilog
93 lines
2.7 KiB
Systemverilog
// Copyright 2011 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module display_char_tb ();
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parameter RASTER_ADDR_WIDTH = 18;
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parameter RASTER_LINE_WIDTH = 640;
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parameter RASTER_DATA_WIDTH = 16;
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parameter FONT_DATA_WIDTH = 24;
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parameter FONT_HEIGHT = 27;
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parameter FONT_ADDR_WIDTH = 12;
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parameter WRITE_DATA = 16'h1234;
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reg clk,arst;
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reg [9:0] raster_x = 20;
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reg [9:0] raster_y = 20;
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reg [7:0] char_select = 8'h1;
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wire busy;
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reg start_write = 1'b1;
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wire [RASTER_ADDR_WIDTH-1:0] raster_addr;
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wire [RASTER_DATA_WIDTH-1:0] raster_data;
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reg [15:0] wdata = 16'h1234;
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wire raster_we;
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display_char dut
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(
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.*
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);
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////////////////////////////////
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// faux raster
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////////////////////////////////
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reg [RASTER_LINE_WIDTH * 100: 0 ] raster;
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always @(posedge clk or posedge arst) begin
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if (arst) raster <= 0;
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else begin
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if (raster_we) raster [raster_addr] <= |raster_data;
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end
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end
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integer fil,x,y;
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always @(negedge busy) begin
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$display ("Frame dump...");
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fil =$fopen ("frame.bin");
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for (y=0; y<100; y=y+1) begin
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for (x=0; x<RASTER_LINE_WIDTH; x=x+1) begin
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$fwriteh (fil,raster[y*RASTER_LINE_WIDTH+x]);
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end
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$fwrite (fil,"\n");
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end
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$fclose (fil);
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end
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////////////////////////////////
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// clock driver
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////////////////////////////////
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initial begin
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clk = 0;
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arst = 0;
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#1 arst = 1'b1;
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@(negedge clk);
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arst = 0;
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end
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always begin
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#5 clk = ~clk;
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end
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endmodule
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