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89 lines
3.1 KiB
Verilog
89 lines
3.1 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module ycbcr_to_rgb (
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y,cb,cr,
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red,green,blue,
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clk
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);
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input clk;
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input [7:0] y,cb,cr;
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output reg [7:0] red,green,blue;
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// offset the inputs
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reg signed [8:0] adj_y,adj_cb,adj_cr;
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always @(posedge clk) begin
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adj_y <= y - 8'd16;
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adj_cr <= cr - 8'd128;
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adj_cb <= cb - 8'd128;
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end
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// scaling constants from standard formulas
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// nominal Y is 16 to 235
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// nominal C's are 16-240 with 128 at zero
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//
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wire signed [8:0] const0 = 9'd149; // 1.164 * 128
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wire signed [8:0] const1 = 9'd204; // 1.596 * 128
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wire signed [8:0] const2 = - 9'd104; // 0.813 * 128
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wire signed [8:0] const3 = - 9'd50; // 0.392 * 128
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//wire signed [8:0] const4 = (10)'d258; // 2.017 * 128
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// const 4 should be 258, which doesn't fit the 9x9 size.
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// do some shifted additions to fake it.
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// multipliers - 9x9 is a natural building block
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reg signed [17:0] product_a, product_b, product_c,
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product_d, product_e;
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always @(posedge clk) begin
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product_a <= const0 * adj_y;
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product_b <= const1 * adj_cr;
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product_c <= const2 * adj_cr;
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product_d <= const3 * adj_cb;
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product_e <= {adj_cb[8],adj_cb[8:0],8'b0} +
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{{9{adj_cb[8]}},adj_cb[7:0],1'b0};
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end
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// summation - 17 selected by simulation
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reg signed [17:0] sum_red, sum_green, sum_blue;
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always @(posedge clk) begin
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sum_red <= product_a + product_b;
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sum_green <= product_a + product_c + product_d;
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sum_blue <= product_a + product_e;
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end
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// saturation
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always @(posedge clk) begin
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red <= sum_red[17] ? 8'h0 :
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(sum_red[15] | sum_red[16]) ? 8'hff :
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sum_red [14:7];
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green <= sum_green[17] ? 8'h0 :
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(sum_green[15] | sum_green[16]) ? 8'hff :
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sum_green [14:7];
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blue <= sum_blue[17] ? 8'h0 :
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(sum_blue[15] | sum_blue[16]) ? 8'hff :
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sum_blue [14:7];
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end
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endmodule
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