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91 lines
2.5 KiB
Systemverilog
91 lines
2.5 KiB
Systemverilog
//------------------------------------------------------------------------------
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// adder_tree.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO -------------------------------------------------------------------------
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// Pipelined tree adder with parametrized input width written in System Verilog
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//
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// - Number of inputs is NOT required to be power of two
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// - This code can generate entirely combinational circuit with minimal editing
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//
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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adder_tree #(
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.INPUTS_NUM( 125 ),
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.IDATA_WIDTH( 16 )
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) AT1 (
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.clk( ),
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.nrst( ),
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.idata( ),
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.odata( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module adder_tree #(
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parameter INPUTS_NUM = 125,
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parameter IDATA_WIDTH = 16,
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parameter STAGES_NUM = $clog2(INPUTS_NUM),
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parameter INPUTS_NUM_INT = 2 ** STAGES_NUM,
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parameter ODATA_WIDTH = IDATA_WIDTH + STAGES_NUM
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)(
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input clk,
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input nrst,
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input logic [INPUTS_NUM-1:0][IDATA_WIDTH-1:0] idata,
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output logic [ODATA_WIDTH-1:0] odata
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);
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logic [STAGES_NUM:0][INPUTS_NUM_INT-1:0][ODATA_WIDTH-1:0] data;
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// generating tree
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genvar stage, adder;
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generate
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for( stage = 0; stage <= STAGES_NUM; stage++ ) begin: stage_gen
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localparam ST_OUT_NUM = INPUTS_NUM_INT >> stage;
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localparam ST_WIDTH = IDATA_WIDTH + stage;
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if( stage == '0 ) begin
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// stege 0 is actually module inputs
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for( adder = 0; adder < ST_OUT_NUM; adder++ ) begin: inputs_gen
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always_comb begin
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if( adder < INPUTS_NUM ) begin
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data[stage][adder][ST_WIDTH-1:0] <= idata[adder][ST_WIDTH-1:0];
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data[stage][adder][ODATA_WIDTH-1:ST_WIDTH] <= '0;
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end else begin
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data[stage][adder][ODATA_WIDTH-1:0] <= '0;
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end
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end // always_comb
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end // for
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end else begin
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// all other stages hold adders outputs
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for( adder = 0; adder < ST_OUT_NUM; adder++ ) begin: adder_gen
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//always_comb begin // is also possible here
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always_ff@(posedge clk) begin
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if( ~nrst ) begin
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data[stage][adder][ODATA_WIDTH-1:0] <= '0;
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end else begin
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data[stage][adder][ST_WIDTH-1:0] <=
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data[stage-1][adder*2][(ST_WIDTH-1)-1:0] +
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data[stage-1][adder*2+1][(ST_WIDTH-1)-1:0];
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end
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end // always
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end // for
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end // if stage
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end // for
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endgenerate
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assign odata = data[STAGES_NUM][0];
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endmodule
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