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24 lines
792 B
Plaintext
24 lines
792 B
Plaintext
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Gowin benchmark project
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=========================
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Konstantin Pavlov, pavlovconst@gmail.com
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This project uses dynamic_delay.sv module to model both high-register count and
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combinational-intensive design.
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To see total time spent for the compilation please use some sort of external
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timer. This will give you some quantitive charachteristic of
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your environment processing power.
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You can also compare how different machines and environments deal with this
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typical design when compiling for FPGAs. I use only pure RTL code here with
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intention to leave an opportunity to compare compilation time across all
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possible IDE`s and even across all FPGA vendors.
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"quartus_benchmark" is a similar project for Altera / Intel devices
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"vivado_benchmark" is a similar project for Xilinx / AMD devices
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