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22 lines
701 B
Plaintext
22 lines
701 B
Plaintext
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Quartus benchmark project
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=========================
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Konstantin Pavlov, pavlovconst@gmail.com
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This project uses dynamic_delay.sv module to model both high-register count and
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combinational-intensive design.
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See Quartus "Messages" tab for TOTAL time spent for compilation. This will give
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you some quantitive charachteristic of your environment processing power.
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You can also compare how different machines and environments deal with this
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typical design when compiling for FPGAs. I use only pure RTL code here with
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intention to leave an opportunity to compare compilation time across all
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possible IDE`s and even across all FPGA vendors.
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"vivado_benchmark" is a similar project for Xilinx devices
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