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36 lines
836 B
Systemverilog
36 lines
836 B
Systemverilog
//------------------------------------------------------------------------------
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// bin2gray.sv
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Gray code to binary converter
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// Combinational design
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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bin2gray #(
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.WIDTH( 32 )
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) BG1 (
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.bin_in( ),
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.gray_out( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module bin2gray #( parameter
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WIDTH = 32
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)(
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input [WIDTH-1:0] bin_in,
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output logic[WIDTH-1:0] gray_out
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);
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always_comb begin
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gray_out[WIDTH-1:0] = bin_in[WIDTH-1:0] ^ ( bin_in[WIDTH-1:0] >> 1 );
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end
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endmodule
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