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70 lines
1.7 KiB
Verilog
70 lines
1.7 KiB
Verilog
//------------------------------------------------------------------------------
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// delay.v
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO -------------------------------------------------------------------------
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// Static Delay for arbitrary signal
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// (simplified Verilog version, see ./delay.sv for advanced features)
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//
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// Another equivalent names for this module:
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// conveyor.sv
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// synchronizer.sv
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//
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// Tip for Xilinx-based implementations: Leave nrst=1'b1 and ena=1'b1 on
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// purpose of inferring Xilinx`s SRL16E/SRL32E primitives
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//
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// CAUTION: delay module is widely used for synchronizing signals across clock
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// domains. When synchronizing, please exclude input data paths from timing
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// analysis manually by writing appropriate set_false_path SDC constraint
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//
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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delay #(
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.LENGTH( 2 ),
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.WIDTH( 1 )
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) S1 (
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.clk( clk ),
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.nrst( 1'b1 ),
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.ena( 1'b1 ),
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.in( ),
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.out( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module delay #( parameter
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LENGTH = 2, // delay/synchronizer chain length
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WIDTH = 1 // signal width
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)(
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input clk,
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input nrst,
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input ena,
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input [WIDTH-1:0] in,
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output [WIDTH-1:0] out
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);
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reg [LENGTH:1][WIDTH-1:0] data = 0;
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always @(posedge clk) begin
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integer i;
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if( ~nrst ) begin
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data <= 0;
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end else if( ena ) begin
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for( i=LENGTH-1; i>0; i=i-1 ) begin
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data[i+1][WIDTH-1:0] <= data[i][WIDTH-1:0];
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end
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data[1][WIDTH-1:0] <= in[WIDTH-1:0];
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end
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end
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assign out[WIDTH-1:0] = data[LENGTH][WIDTH-1:0];
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endmodule
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