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88 lines
2.4 KiB
Systemverilog
Executable File
88 lines
2.4 KiB
Systemverilog
Executable File
//--------------------------------------------------------------------------------
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// dynamic_delay.sv
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// Dynamic delay for arbitrary signal.
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//
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// Incoming data elements have WIDTH bits each. Module does serialization of
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// input data and outputs flattened bits, based on provided selector value.
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// You can perform delays bit-wize, not just element-wize.
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//
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// CAUTION: Be careful selecting last, most-delayed "WIDTH" number of bits.
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// The module intentionally does NOT implement "out of range"
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// checks. Please handle them externally.
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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dynamic_delay #(
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.LENGTH( 3 ),
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.WIDTH( 4 )
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) M (
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.clk( clk ),
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.nrst( nrst ),
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.ena( 1'b1 ),
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.in( in_data[3:0] ),
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.sel( sel[3:0] ),
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.out( out_data[3:0] )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module dynamic_delay #( parameter
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LENGTH = 63, // maximum delay chain length
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WIDTH = 4, // data width
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SEL_W = $clog2( (LENGTH+1)*WIDTH ) // output selector width
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// plus one is for zero delay element
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)(
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input clk,
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input nrst,
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input ena,
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input [WIDTH-1:0] in, // input data
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// bit in[0] is the "oldest" one
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// bit in[WIDTH] is considered the most recent
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input [SEL_W-1:0] sel, // output selector
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output logic [WIDTH-1:0] out // output data
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);
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logic [(LENGTH+1)-1:0][WIDTH-1:0] data = '0;
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// packed vector includes extra bits
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logic [(LENGTH+1)*WIDTH-1:0] pack_data;
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assign pack_data[(LENGTH+1)*WIDTH-1:0] = data;
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integer i;
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always_ff @(posedge clk) begin
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if( ~nrst ) begin
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// reset all data except zero element
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for( i=1; i<(LENGTH+1); i=i+1 ) begin
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data[i][WIDTH-1:0] <= '0;
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end
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end else if (ena) begin
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for( i=1; i<(LENGTH+1); i=i+1 ) begin
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data[i][WIDTH-1:0] <= data[i-1][WIDTH-1:0];
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end
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end
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end
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integer j;
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always_comb begin
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// zero element assignment
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data[0][WIDTH-1:0] <= in[WIDTH-1:0];
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// output selector, sel==0 gives non-delayed output
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for( j=0; j<WIDTH; j=j+1 ) begin
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out[j] <= pack_data[sel[SEL_W-1:0]+j];
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end
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end
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endmodule
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