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101 lines
2.8 KiB
Systemverilog
Executable File
101 lines
2.8 KiB
Systemverilog
Executable File
//------------------------------------------------------------------------------
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// edge_detect.sv
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Edge detector, ver.4
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//
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// (new!) Added WIDTH parameter to simplify instantiating arrays of edge detectors
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// (new!) Made reset to be asynchronous
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//
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// Added parameter to select combinational implementation (zero clocks delay)
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// or registered implementation (one clocks delay)
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//
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// In case when "in" port has toggle rate 100% (changes every clock period)
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// "rising" and "falling" outputs will completely replicate input
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// "both" output will be always active in this case
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//
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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edge_detect #(
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.WIDTH( 32 ),
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.REGISTER_OUTPUTS( 1'b1 )
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) in_ed (
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.clk( clk ),
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.anrst( 1'b1 ),
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.in( in[31:0] ),
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.rising( in_rise[31:0] ),
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.falling( ),
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.both( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module edge_detect #( parameter
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bit [7:0] WIDTH = 1, // signal width
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bit [0:0] REGISTER_OUTPUTS = 1'b0 // 0 - comb. implementation (default)
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// 1 - registered implementation
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)(
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input clk,
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input anrst,
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input [WIDTH-1:0] in,
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output logic [WIDTH-1:0] rising,
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output logic [WIDTH-1:0] falling,
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output logic [WIDTH-1:0] both
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);
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// data delay line
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logic [WIDTH-1:0] in_d = '0;
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always_ff @(posedge clk or negedge anrst) begin
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if ( ~anrst ) begin
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in_d[WIDTH-1:0] <= '0;
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end else begin
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in_d[WIDTH-1:0] <= in[WIDTH-1:0];
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end
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end
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logic [WIDTH-1:0] rising_comb;
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logic [WIDTH-1:0] falling_comb;
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logic [WIDTH-1:0] both_comb;
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always_comb begin
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rising_comb[WIDTH-1:0] = {WIDTH{anrst}} & (in[WIDTH-1:0] & ~in_d[WIDTH-1:0]);
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falling_comb[WIDTH-1:0] = {WIDTH{anrst}} & (~in[WIDTH-1:0] & in_d[WIDTH-1:0]);
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both_comb[WIDTH-1:0] = {WIDTH{anrst}} & (rising_comb[WIDTH-1:0] | falling_comb[WIDTH-1:0]);
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end
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generate
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if( REGISTER_OUTPUTS==1'b0 ) begin
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// combinational outputs, no delay
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always_comb begin
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rising[WIDTH-1:0] = rising_comb[WIDTH-1:0];
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falling[WIDTH-1:0] = falling_comb[WIDTH-1:0];
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both[WIDTH-1:0] = both_comb[WIDTH-1:0];
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end // always
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end else begin
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// registered outputs, 1 cycle delay
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always_ff @(posedge clk or negedge anrst) begin
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if( ~anrst ) begin
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rising[WIDTH-1:0] <= '0;
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falling[WIDTH-1:0] <= '0;
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both[WIDTH-1:0] <= '0;
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end else begin
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rising[WIDTH-1:0] <= rising_comb[WIDTH-1:0];
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falling[WIDTH-1:0] <= falling_comb[WIDTH-1:0];
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both[WIDTH-1:0] <= both_comb[WIDTH-1:0];
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end // always
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end // if
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end // end else
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endgenerate
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endmodule
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