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44 lines
886 B
Verilog
44 lines
886 B
Verilog
//--------------------------------------------------------------------------------
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// encoder.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// Digital encoder
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/*encoder E1(
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.clk(),
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.nrst(),
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.incA(),
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.incB(),
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.plus1(),
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.minus1()
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);*/
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module encoder(clk,nrst,incA,incB,plus1,minus1);
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input wire clk;
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input wire nrst;
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input wire incA, incB; // present input values
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output reg plus1 = 0, minus1 = 0;
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reg bufA = 0, bufB = 0; // previous inputvalues
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always @ (posedge clk) begin
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if (~nrst) begin
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bufA <= 0;
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bufB <= 0;
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plus1 <= 0;
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minus1 <= 0;
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end
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else begin
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plus1 <= (bufA^incB)&~(incA^bufB);
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minus1 <= (incA^bufB)&~(bufA^incB);
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bufA <= incA;
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bufB <= incB;
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end // if
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end
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endmodule |