This website requires JavaScript.
Explore
Help
Sign In
FPGA
/
basic_verilog
Watch
1
Star
0
Fork
0
You've already forked basic_verilog
mirror of
https://github.com/pConst/basic_verilog.git
synced
2025-01-14 06:42:54 +08:00
Code
Issues
Releases
Wiki
Activity
basic_verilog
/
example_projects
History
Konstantin Pavlov
e1412c080b
Change some pins to I and IO for convinience
2024-07-02 16:01:04 +03:00
..
gowin_fmax_test_prj_template_v1
Added Fmax test project for Gowin
2022-05-16 18:56:57 +03:00
quartus_fmax_test_prj_template_v3
Added Fmax test projects for Quartus and for Vivado
2022-05-01 15:03:04 +03:00
quartus_test_prj_template_v4
Updated test projects to support dev boards
2022-04-05 18:35:04 +03:00
testbench_template_tb
Fixed Questa support in testbench_template
2022-12-29 17:01:18 +03:00
vitis_hls_test_prj_template_v2
Added sample code
2023-03-29 13:07:39 +03:00
vivado_fmax_test_prj_template_v3
Updated scripts
2022-06-06 09:52:10 +03:00
vivado_test_prj_template_v3
Change some pins to I and IO for convinience
2024-07-02 16:01:04 +03:00
скрипт компилирует до тех пор, пока не сойдутся тайминги.txt
Added sample code
2023-03-29 13:07:39 +03:00