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110 lines
2.7 KiB
Systemverilog
110 lines
2.7 KiB
Systemverilog
//------------------------------------------------------------------------------
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// fast_counter.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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//
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// - This is a synthetic fast counter which appears faster than a standard one
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// generated from pure Verilog code
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//
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// - My tests show that it is on average 30MHz faster in direct comparisons for
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// counters from 5 to 32 bit widths in Cyclone V
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//
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// - Use this counter only when counter performance is your last and ultimate
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// resort to conquer timings. Fast counter is area-unefficient thing.
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//
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// - fast_counter_iterative_test project in the repo shows fast counter`s advantage
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// https://github.com/pConst/basic_verilog/fast_counter_iterative_test/
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//
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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fast_counter #(
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.WIDTH( 14 )
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) fc (
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.clk( clk ),
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.set( ), // highest priority operation, use it like a reset also
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.set_val( ),
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.dec( ),
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.q( ),
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.q_is_zero( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module fast_counter #( parameter
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WIDTH = 8
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)(
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input clk,
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input set,
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input [WIDTH-1:0] set_val,
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input dec,
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output [WIDTH-1:0] q,
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output q_is_zero
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);
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const logic [5:0][15:0] lsb_bits_init = { 16'b0000000000000001,
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16'b1000000000000000,
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16'b1111111100000000,
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16'b1111000011110000,
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16'b1100110011001100,
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16'b1010101010101010 };
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logic [WIDTH-4-1:0] msb_bits = '0;
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logic [5:0][15:0] lsb_bits = lsb_bits_init;
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logic [16*6-1:0] lsb_bits_flat;
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assign lsb_bits_flat[16*6-1:0] = lsb_bits;
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integer i,j;
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always_ff @(posedge clk) begin
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if( set ) begin
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msb_bits[WIDTH-4-1:0] <= set_val[WIDTH-1:4];
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for( i=0; i<6; i++ ) begin
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for( j=0; j<16; j++ ) begin
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lsb_bits[i][j] <= lsb_bits_init[i][(set_val[3:0]+j) % 16];
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end
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end
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end else if( dec ) begin
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if( lsb_bits[5][0] ) begin
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msb_bits[WIDTH-4-1:0] <= msb_bits[WIDTH-4-1:0] - 1'b1;
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end
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for( i=0; i<6; i++ ) begin
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for( j=0; j<16; j++ ) begin
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if( j==0 ) begin
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lsb_bits[i][j] <= lsb_bits[i][15];
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end else begin
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lsb_bits[i][j] <= lsb_bits[i][j-1];
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end
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end
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end
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end
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end
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assign q[WIDTH-1:4] = msb_bits[WIDTH-4-1:0];
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assign q[3] = lsb_bits[3][0],
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q[2] = lsb_bits[2][0],
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q[1] = lsb_bits[1][0],
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q[0] = lsb_bits[0][0];
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assign q_is_zero = ~|q[WIDTH-1:0];
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endmodule
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