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133 lines
3.2 KiB
Systemverilog
133 lines
3.2 KiB
Systemverilog
//------------------------------------------------------------------------------
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// fifo_operator.sv
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Performs custom operation on data words from multiple FIFOs and stores
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// result to a single output FIFO.
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// Reads only if ALL input FIFOs have data.
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// Source code could be easily adapted to apply any operator on input data.
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//
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// See also fifo_combiner.sv
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//
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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fifo_operator #(
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.WIDTH( 2 ),
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.FWFT_MODE( "TRUE" ),
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.DATA_W( 32 )
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) FO1 (
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.clk( ),
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.nrst( ),
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.r_empty( ),
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.r_req( ),
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.r_data( ),
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.w_full( ), // connect to "almost_full" if FWFT_MODE="FALSE"
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.w_req( ),
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.w_data( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module fifo_operator #( parameter
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WIDTH = 2, // number of input fifo ports to opeate on
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WIDTH_W = clogb2(WIDTH), // input port index width
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FWFT_MODE = "TRUE", // "TRUE" - first word fall-trrough" mode
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// "FALSE" - normal fifo mode
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DATA_W = 32 // data field width
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)(
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input clk, // clock
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input nrst, // inverted reset
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// input ports
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input [WIDTH-1:0] r_empty,
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output [WIDTH-1:0] r_req,
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input [WIDTH-1:0][DATA_W-1:0] r_data,
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// output port
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input w_full,
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output logic w_req,
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output logic [DATA_W-1:0] w_data
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);
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logic r_valid;
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assign r_valid = ~|r_empty && ~w_full;
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assign r_req[WIDTH-1:0] = {WIDTH{r_valid}};
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// buffering read data
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logic r_valid_d1 = 1'b0;
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logic [WIDTH-1:0][DATA_W-1:0] r_data_d1 = '0;
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always_ff @(posedge clk) begin
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if ( ~nrst ) begin
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r_valid_d1 <= 1'b0;
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r_data_d1[WIDTH-1:0] <= '0;
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end else begin
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r_valid_d1 <= r_valid;
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r_data_d1[WIDTH-1:0] <= r_data[WIDTH-1:0];
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end
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end
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// routing data to write port
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generate
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if( FWFT_MODE == "TRUE" ) begin
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always_comb begin
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if ( ~nrst ) begin
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w_req = 1'b0;
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w_data[DATA_W-1:0] = '0;
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end else begin
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if( r_valid ) begin
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w_req = 1'b1;
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w_data[DATA_W-1:0] = operator(r_data);
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end else begin
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w_req = 1'b0;
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w_data[DATA_W-1:0] = '0;
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end
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end
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end
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end else if( FWFT_MODE == "FALSE" ) begin
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always_comb begin
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if ( ~nrst ) begin
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w_req = 1'b0;
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w_data[DATA_W-1:0] = '0;
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end else begin
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if( r_valid_d1 ) begin
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w_req = 1'b1;
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w_data[DATA_W-1:0] = operator(r_data_d1);
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end else begin
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w_req = 1'b0;
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w_data[DATA_W-1:0] = '0;
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end
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end
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end
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end // FWFT_MODE
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endgenerate
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// bitwize OR operator, as an example
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function [DATA_W-1:0] operator (
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input [WIDTH-1:0][DATA_W-1:0] data
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);
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integer i;
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operator[DATA_W-1:0] = '0;
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for( i=0; i<WIDTH; i=i+1 ) begin
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operator[DATA_W-1:0] = operator[DATA_W-1:0] | data[i];
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end
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endfunction
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`include "clogb2.svh"
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endmodule
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