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44 lines
1.2 KiB
Systemverilog
Executable File
44 lines
1.2 KiB
Systemverilog
Executable File
//------------------------------------------------------------------------------
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// fifo_single_clock_reg_v2_init.svh
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Initialization statements example for fifo_single_clock_reg_v2 fifo
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//
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data[0] <= 32'hAAAA;
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data[1] <= 32'h0001;
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data[2] <= 32'h0002;
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data[3] <= 32'h0003;
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data[4] <= 32'h0004;
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data[5] <= 32'h0005;
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data[6] <= 32'h0006;
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data[7] <= 32'h0007;
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data[8] <= 32'hBBBB;
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data[9] <= 32'h0001;
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data[10] <= 32'h0002;
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data[11] <= 32'h0003;
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data[12] <= 32'h0004;
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data[13] <= 32'h0005;
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data[14] <= 32'h0006;
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data[15] <= 32'h0007;
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data[16] <= 32'hCCCC;
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data[17] <= 32'h0001;
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data[18] <= 32'h0002;
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data[19] <= 32'h0003;
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data[20] <= 32'h0004;
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data[21] <= 32'h0005;
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data[22] <= 32'h0006;
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data[23] <= 32'h0007;
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data[24] <= 32'hDDDD;
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data[25] <= 32'h0001;
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data[26] <= 32'h0002;
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data[27] <= 32'h0003;
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data[28] <= 32'h0004;
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data[29] <= 32'h0005;
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data[30] <= 32'h0006;
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data[31] <= 32'h0007;
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