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https://github.com/pConst/basic_verilog.git
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117 lines
2.0 KiB
Systemverilog
117 lines
2.0 KiB
Systemverilog
//------------------------------------------------------------------------------
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// gray_tb.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// testbench for bin2gray and gray2bin module
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`timescale 1ns / 1ps
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module gray_tb();
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logic clk200;
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initial begin
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#0 clk200 = 1'b0;
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forever
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#2.5 clk200 = ~clk200;
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end
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logic rst;
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initial begin
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#0 rst = 1'b0;
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#10.2 rst = 1'b1;
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#5 rst = 1'b0;
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//#10000;
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forever begin
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#9985 rst = ~rst;
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#5 rst = ~rst;
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end
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end
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logic nrst;
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assign nrst = ~rst;
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logic rst_once;
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initial begin
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#0 rst_once = 1'b0;
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#10.2 rst_once = 1'b1;
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#5 rst_once = 1'b0;
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end
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logic nrst_once;
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assign nrst_once = ~rst_once;
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logic [31:0] DerivedClocks;
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clk_divider #(
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.WIDTH( 32 )
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) cd1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.ena( 1'b1 ),
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.out( DerivedClocks[31:0] )
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);
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logic [31:0] E_DerivedClocks;
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edge_detect ed1[31:0] (
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.clk( {32{clk200}} ),
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.nrst( {32{nrst_once}} ),
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.in( DerivedClocks[31:0] ),
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.rising( E_DerivedClocks[31:0] ),
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.falling( ),
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.both( )
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);
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logic [15:0] RandomNumber1;
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c_rand rng1 (
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.clk( clk200 ),
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.rst( rst_once ),
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.reseed( 1'b0 ),
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.seed_val( DerivedClocks[31:0] ),
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.out( RandomNumber1[15:0] )
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);
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logic start;
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initial begin
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#0 start = 1'b0;
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#100 start = 1'b1;
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#20 start = 1'b0;
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end
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// Module under test ==========================================================
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`define WIDTH 32
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logic [`WIDTH-1:0] bin = 0;
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always_ff @(posedge clk200) begin
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if(~nrst_once) begin
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bin[`WIDTH-1:0] <= 0;
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end else begin
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bin[`WIDTH-1:0] <= bin[`WIDTH-1:0] + 1'b1;
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end
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end
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logic [`WIDTH-1:0] gray;
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bin2gray #(
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.WIDTH( `WIDTH )
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) BG1 (
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.bin_in( bin[`WIDTH-1:0] ),
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.gray_out( gray[`WIDTH-1:0] )
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);
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logic [`WIDTH-1:0] bin2;
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gray2bin #(
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.WIDTH( `WIDTH )
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) GB1 (
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.gray_in( gray[`WIDTH-1:0] ),
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.bin_out( bin2[`WIDTH-1:0] )
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);
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//assert property
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// (bin[`WIDTH-1:0] == bin2[`WIDTH-1:0])
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//else $error("It's gone wrong");
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endmodule
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