FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-14 06:42:54 +08:00
Code Issues Releases Wiki Activity
basic_verilog/interfaces
History
Konstantin Pavlov 46e79a0d34 Added Wishbone interface
2023-10-29 13:57:06 +03:00
..
axi4_if.sv
Added Wishbone interface
2023-10-29 13:57:06 +03:00
axis_if.sv
Added Wishbone interface
2023-10-29 13:57:06 +03:00
wb_if.sv
Added Wishbone interface
2023-10-29 13:57:06 +03:00