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62 lines
1.1 KiB
Systemverilog
62 lines
1.1 KiB
Systemverilog
//------------------------------------------------------------------------------
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// axis_if.sv
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// AXI4-Stream instantiation
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//
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interface axis_if #( parameter
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DATA_W = 32,
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ID_W = 8,
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USER_W = 0
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);
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localparam KEEP_W = DATA_W/8;
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logic [DATA_W-1:0] tdata;
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logic [ ID_W-1:0] tdest;
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logic [ ID_W-1:0] tid;
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logic [KEEP_W-1:0] tkeep;
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logic tlast;
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logic tready;
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logic [USER_W-1:0] tuser;
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logic tvalid;
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modport master_mp(
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input tready,
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output tdata,
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output tdest,
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output tid,
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output tkeep,
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output tlast,
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output tuser,
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output tvalid
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);
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modport slave_mp(
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input tdata,
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input tdest,
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input tid,
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input tkeep,
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input tlast,
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input tuser,
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input tvalid,
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output tready
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);
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endinterface
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