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48 lines
967 B
Systemverilog
48 lines
967 B
Systemverilog
//------------------------------------------------------------------------------
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// leave_one_hot.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO -------------------------------------------------------------------------
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// Completely combinational module that leaves only lowest hot bit
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// compared to input vector
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//
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// For example 16'b1101_0000 becomes 8'b0001_0000
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// 16'b1101_0010 becomes 8'b0000_0010
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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leave_one_hot #(
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.WIDTH( 32 )
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) OH1 (
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.in( ),
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.out( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module leave_one_hot #( parameter
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WIDTH = 32
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)(
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input [WIDTH-1:0] in,
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output logic [WIDTH-1:0] out
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);
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genvar i;
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generate
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for( i=1; i<WIDTH; i++ ) begin : gen_for
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always_comb begin
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out[i] <= in[i] && ~( |in[(i-1):0] );
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end
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end // for i
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endgenerate
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assign out[0] = in[0];
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endmodule
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