mirror of
https://github.com/pConst/basic_verilog.git
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157 lines
2.8 KiB
Systemverilog
157 lines
2.8 KiB
Systemverilog
//------------------------------------------------------------------------------
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// lifo_tb.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// testbench for lifo.sv module
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//
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`timescale 1ns / 1ps
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module lifo_tb();
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logic clk200;
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initial begin
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#0 clk200 = 1'b0;
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forever
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#2.5 clk200 = ~clk200;
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end
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// external device "asynchronous" clock
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logic clk33;
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initial begin
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#0 clk33 = 1'b0;
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forever
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#15.151 clk33 = ~clk33;
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end
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logic rst;
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initial begin
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#0 rst = 1'b0;
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#10.2 rst = 1'b1;
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#5 rst = 1'b0;
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//#10000;
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forever begin
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#9985 rst = ~rst;
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#5 rst = ~rst;
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end
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end
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logic nrst;
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assign nrst = ~rst;
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logic rst_once;
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initial begin
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#0 rst_once = 1'b0;
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#10.2 rst_once = 1'b1;
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#5 rst_once = 1'b0;
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end
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logic nrst_once;
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assign nrst_once = ~rst_once;
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logic [31:0] DerivedClocks;
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clk_divider #(
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.WIDTH( 32 )
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) cd1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.ena( 1'b1 ),
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.out( DerivedClocks[31:0] )
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);
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logic [31:0] E_DerivedClocks;
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edge_detect ed1[31:0] (
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.clk( {32{clk200}} ),
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.nrst( {32{nrst_once}} ),
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.in( DerivedClocks[31:0] ),
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.rising( E_DerivedClocks[31:0] ),
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.falling( ),
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.both( )
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);
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logic [15:0] RandomNumber1;
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c_rand rng1 (
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.clk(clk200),
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.rst(rst_once),
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.reseed(1'b0),
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.seed_val(DerivedClocks[31:0]),
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.out( RandomNumber1[15:0] )
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);
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logic start;
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initial begin
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#0 start = 1'b0;
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#100 start = 1'b1;
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#20 start = 1'b0;
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end
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// Module under test ==========================================================
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// comment or uncomment to test FWFT and normal fifo modes
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//`define TEST_FWFT yes
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// comment or uncomment to sweep-test or random test
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`define TEST_SWEEP yes
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logic full1, empty1;
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logic full1_d1, empty1_d1;
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logic direction1 = 1'b0;
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always_ff @(posedge clk200) begin
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if( ~nrst ) begin
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direction1 <= 1'b0;
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end else begin
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// sweep logic
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if( full1_d1 ) begin
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direction1 <= 1'b1;
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end else if( empty1_d1 ) begin
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direction1 <= 1'b0;
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end
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// these signals allow "erroring" requests testing:
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// - reads from the empty fifo
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// - writes to the filled fifo
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full1_d1 <= full1;
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empty1_d1 <= empty1;
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end
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end
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logic [3:0] cnt1;
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logic [15:0] data_out1;
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lifo #(
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`ifdef TEST_FWFT
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.FWFT_MODE( "TRUE" ),
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`else
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.FWFT_MODE( "FALSE" ),
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`endif
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.DEPTH( 8 ),
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.DATA_W( 16 )
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) LF1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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`ifdef TEST_SWEEP
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.w_req( ~direction1 && &RandomNumber1[10] ),
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.w_data( RandomNumber1[15:0] ),
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.r_req( direction1 && &RandomNumber1[10] ),
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.r_data( data_out1[15:0] ),
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`else
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.w_req( &RandomNumber1[10:9] ),
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.w_data( RandomNumber1[15:0] ),
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.r_req( &RandomNumber1[8:7] ),
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.r_data( data_out1[15:0] ),
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`endif
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.cnt( cnt1[3:0] ),
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.empty( empty1 ),
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.full( full1 )
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);
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endmodule
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