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92 lines
3.9 KiB
Verilog
92 lines
3.9 KiB
Verilog
//------------------------------------------------------------------------------
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// pack_unpack_array.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// This module defines macros for pacing and unpacking 2D and 3D vectors
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// to pass them through parent module`s ports
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// Verilog-2001 standard does not allow multi-dimensional vectors to appear in
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// ports. These macros allow to bypass the violation
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genvar pk_i;
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genvar pk_j;
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`define PACK_ARRAY_2D(PK_DIM1,PK_DIM0,PK_SRC,PK_DEST) generate for(pk_i=0; pk_i<(PK_DIM1); pk_i=pk_i+1) begin; assign PK_DEST[((PK_DIM0)*pk_i+((PK_DIM0)-1)):((PK_DIM0)*pk_i)] = PK_SRC[pk_i][((PK_DIM0)-1):0]; end; endgenerate
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`define UNPACK_ARRAY_2D(PK_DIM1,PK_DIM0,PK_DEST,PK_SRC) generate for(pk_i=0; pk_i<(PK_DIM1); pk_i=pk_i+1) begin; assign PK_DEST[pk_i][((PK_DIM0)-1):0] = PK_SRC[((PK_DIM0)*pk_i+(PK_DIM0-1)):((PK_DIM0)*pk_i)]; end; endgenerate
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`define PACK_ARRAY_3D(PK_DIM2,PK_DIM1,PK_DIM0,PK_SRC,PK_DEST) generate for(pk_i=0; pk_i<(PK_DIM1); pk_i=pk_i+1) begin; for(pk_j=0; pk_j<(PK_DIM1); pk_j=pk_j+1) begin; assign PK_DEST[(((PK_DIM1)*pk_j+((PK_DIM1)-1))+((PK_DIM0)*pk_i+((PK_DIM0)-1))):((PK_DIM0)*pk_i)*pk_j] = PK_SRC[pk_j][pk_i][((PK_DIM0)-1):0]; end; end; endgenerate
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`define UNPACK_ARRAY_3D(PK_DIM2,PK_DIM1,PK_DIM0,PK_DEST,PK_SRC) generate for(pk_i=0; pk_i<(PK_DIM1); pk_i=pk_i+1) begin; for(pk_j=0; pk_j<(PK_DIM1); pk_j=pk_j+1) begin; assign PK_DEST[pk_j][pk_i][((PK_DIM0)-1):0] = PK_SRC[(((PK_DIM1)*pk_j+((PK_DIM1)-1))+((PK_DIM0)*pk_i+((PK_DIM0)-1))):((PK_DIM0)*pk_i)*pk_j]; end; end; endgenerate
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// === USAGE EXAMPLE BEGIN =====================================================
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//
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// `include "pack_unpack_array.v"
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//
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// module example (
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// input [63:0] pack_64,
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// output [63:0] pack_64_out
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// );
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//
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// // unpacking arrays
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// wire [7:0] in_2d [7:0];
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// `UNPACK_ARRAY_2D(8,8,pack_64,in_2d)
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// wire [7:0] in_3d [1:0][3:0];
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// `UNPACK_ARRAY_3D(2,4,8,pack_64,in_3d)
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//
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// // working with unpacked arrays
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// wire [7:0] in_3d_modified [1:0][3:0];
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// assign in_3d_modified = ~in_3d;
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//
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// // packing data back
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// `PACK_ARRAY_3D(2,4,8,in_3d_modified,pack_64_out)
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//
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// endmodule
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//
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// === USAGE EXAMPLE END =======================================================
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// === FORMATTED VERSION BEGIN =================================================
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//
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// genvar pk_i;
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// genvar pk_j;
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// `define PACK_ARRAY_2D(PK_DIM1,PK_DIM0,PK_SRC,PK_DEST)
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// generate
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// for(pk_i=0; pk_i<(PK_DIM1); pk_i=pk_i+1) begin;
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// assign PK_DEST[((PK_DIM0)*pk_i+((PK_DIM0)-1)):((PK_DIM0)*pk_i)] =
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// PK_SRC[pk_i][((PK_DIM0)-1):0];
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// end;
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// endgenerate
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// `define UNPACK_ARRAY_2D(PK_DIM1,PK_DIM0,PK_DEST,PK_SRC)
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// generate
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// for(pk_i=0; pk_i<(PK_DIM1); pk_i=pk_i+1) begin;
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// assign PK_DEST[pk_i][((PK_DIM0)-1):0] =
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// PK_SRC[((PK_DIM0)*pk_i+(PK_DIM0-1)):((PK_DIM0)*pk_i)];
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// end;
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// endgenerate
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// `define PACK_ARRAY_3D(PK_DIM2,PK_DIM1,PK_DIM0,PK_SRC,PK_DEST)
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// generate
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// for(pk_i=0; pk_i<(PK_DIM1); pk_i=pk_i+1) begin;
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// for(pk_j=0; pk_j<(PK_DIM1); pk_j=pk_j+1) begin;
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// assign PK_DEST[(((PK_DIM1)*pk_j+((PK_DIM1)-1))+((PK_DIM0)*pk_i+((PK_DIM0)-1))):((PK_DIM0)*pk_i)*pk_j] =
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// PK_SRC[pk_j][pk_i][((PK_DIM0)-1):0];
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// end;
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// end;
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// endgenerate
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// `define UNPACK_ARRAY_3D(PK_DIM2,PK_DIM1,PK_DIM0,PK_DEST,PK_SRC)
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// generate
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// for(pk_i=0; pk_i<(PK_DIM1); pk_i=pk_i+1) begin;
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// for(pk_j=0; pk_j<(PK_DIM1); pk_j=pk_j+1) begin;
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// assign PK_DEST[pk_j][pk_i][((PK_DIM0)-1):0] =
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// PK_SRC[(((PK_DIM1)*pk_j+((PK_DIM1)-1))+((PK_DIM0)*pk_i+((PK_DIM0)-1))):((PK_DIM0)*pk_i)*pk_j];
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// end;
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// end;
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// endgenerate
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//
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// === FORMATTED VERSION END ===================================================
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