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69 lines
2.2 KiB
Verilog
69 lines
2.2 KiB
Verilog
/*
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Copyright (C) 2004-2007 Pablo Bleyer Kocik.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. The name of the author may not be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR IMPLIED
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WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file
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PacoBlaze Call/return stack; single-port RAM.
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*/
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`ifndef PACOBLAZE_STACK_V_
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`define PACOBLAZE_STACK_V_
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`include "pacoblaze_inc.v"
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module `PACOBLAZE_STACK(
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write_enable, update_enable, push_pop, data_in, data_out,
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reset, clk
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);
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input clk, reset, write_enable, update_enable, push_pop; // push:1, pop:0
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input [`stack_width-1:0] data_in;
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output [`stack_width-1:0] data_out;
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reg [`stack_width-1:0] spr[0:`stack_size-1]; // single port ram memory
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reg [`stack_depth-1:0] ptr; // stack pointer
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wire [`stack_depth-1:0] ptr_1 =
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(push_pop) ? ptr + 1 : ptr - 1;
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assign data_out = spr[ptr_1];
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// eliminate undefined data on stack underflow
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integer i;
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initial for(i=0; i<`stack_size; i=i+1) spr[i] <= 0;
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always @(posedge clk)
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if (reset) ptr <= 0;
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else begin
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if (write_enable) spr[ptr] <= data_in;
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if (update_enable) ptr <= ptr_1;
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end
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endmodule
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`endif // PACOBLAZE_STACK_V_
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