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85 lines
2.2 KiB
Systemverilog
85 lines
2.2 KiB
Systemverilog
//------------------------------------------------------------------------------
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// pattern_detect.sv
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Detects data pattern specified by the provided PAT parameter
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//
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// Features capturing WIDTH bits simultaneously in case your data
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// comes in parallel, like in QSPI interface, for example
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//
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// Detects pattern in any possible bit position, supposing that input data
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// is an unaligned bit stream
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//
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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pattern_detect #(
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.DEPTH( 2 ),
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.WIDTH( 16 ),
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// pattern parameters
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.PAT_WIDTH( 5 ), // must be less than DEPTH*WIDTH
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.PAT( 5'b10011 )
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) PD1 (
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.clk( clk ),
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.nrst( nrst ),
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.ena( 1'b1 ),
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.data( data[4:0] ),
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.detected_pos( )
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.detected( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module pattern_detect #( parameter
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DEPTH = 2,
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WIDTH = 16,
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PAT_WIDTH = 5, // must be less than DEPTH*WIDTH
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bit [PAT_WIDTH-1:0] PAT = '1
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)(
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input clk,
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input nrst,
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input ena,
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input [WIDTH-1:0] data,
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output logic detected,
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output logic [DEPTH*WIDTH-1:0] detected_mask
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);
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logic [DEPTH*WIDTH-1:0] sample_buf = '0;
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logic [DEPTH*WIDTH-1:0] ena_buf = '0;
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always @ (posedge clk) begin
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if( ~nrst ) begin
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sample_buf[DEPTH*WIDTH-1:0] <= {DEPTH*WIDTH{1'b0}};
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ena_buf[DEPTH*WIDTH-1:0] <= {DEPTH*WIDTH{1'b0}};
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end else begin
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sample_buf[DEPTH*WIDTH-1:0] <= {sample_buf[DEPTH*WIDTH-WIDTH-1:0],
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data[WIDTH-1:0]};
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ena_buf[DEPTH*WIDTH-1:0] <= {ena_buf[DEPTH*WIDTH-WIDTH-1:0],
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{WIDTH{ena}} };
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end
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end
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always_comb begin
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integer i;
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detected_mask[DEPTH*WIDTH-1:0] = '0;
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for( i=0; i<(DEPTH*WIDTH-PAT_WIDTH); i++ ) begin
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if( sample_buf[i+:PAT_WIDTH] == PAT[PAT_WIDTH-1:0] &&
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ena_buf[i+:PAT_WIDTH]) begin
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detected_mask[i] = 1'b1;
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end
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end
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detected = |detected_mask[DEPTH*WIDTH-1:0];
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end
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endmodule
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