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127 lines
2.3 KiB
Systemverilog
127 lines
2.3 KiB
Systemverilog
//------------------------------------------------------------------------------
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// pattern_detect_tb.sv
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Testbench template with basic clocking, reset and random stimulus signals
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// use this define to make some things differently in simulation
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`define SIMULATION yes
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`timescale 1ns / 1ps
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module pattern_detect_tb();
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logic clk200;
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initial begin
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#0 clk200 = 1'b0;
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forever
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#2.5 clk200 = ~clk200;
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end
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// external device "asynchronous" clock
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logic clk33a;
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initial begin
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#0 clk33a = 1'b0;
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forever
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#7 clk33a = ~clk33a;
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end
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logic clk33;
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//assign clk33 = clk33a;
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always @(*) begin
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clk33 = #($urandom_range(0, 2000)*10ps) clk33a;
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end
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logic rst;
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initial begin
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#0 rst = 1'b0;
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#10.2 rst = 1'b1;
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#5 rst = 1'b0;
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//#10000;
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forever begin
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#9985 rst = ~rst;
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#5 rst = ~rst;
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end
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end
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logic nrst;
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assign nrst = ~rst;
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logic rst_once;
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initial begin
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#0 rst_once = 1'b0;
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#10.2 rst_once = 1'b1;
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#5 rst_once = 1'b0;
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end
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logic nrst_once;
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assign nrst_once = ~rst_once;
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logic [31:0] clk200_div;
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clk_divider #(
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.WIDTH( 32 )
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) cd1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.ena( 1'b1 ),
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.out( clk200_div[31:0] )
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);
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logic [31:0] clk200_div_rise;
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edge_detect ed1[31:0] (
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.clk( {32{clk200}} ),
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.anrst( {32{nrst_once}} ),
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.in( clk200_div[31:0] ),
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.rising( clk200_div_rise[31:0] ),
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.falling( ),
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.both( )
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);
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logic [31:0] rnd_data;
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always_ff @(posedge clk200) begin
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if( ~nrst_once ) begin
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rnd_data[31:0] <= $random( 1 ); // seeding
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end else begin
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rnd_data[31:0] <= $random;
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end
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end
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logic start;
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initial begin
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#0 start = 1'b0;
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#100 start = 1'b1;
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#20 start = 1'b0;
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end
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//initial begin
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// #1000 $finish;
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//end
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// Module under test ===========================================================
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logic [15:0] detected;
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logic [15:0][9:0] detected_mask;
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pattern_detect #(
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.DEPTH( 5 ),
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.WIDTH( 2 ),
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.PAT_WIDTH( 7 ),
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.PAT( 7'b1_11_00_11 )
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) pd [15:0] (
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.clk( {16{clk200}} ),
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.nrst( {16{nrst_once}} ),
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.ena( '1 ),
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.data( rnd_data[31:0] ),
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.detected( detected[15:0] ),
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.detected_mask( detected_mask )
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);
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endmodule
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