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97 lines
3.5 KiB
Systemverilog
97 lines
3.5 KiB
Systemverilog
//------------------------------------------------------------------------------
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// prbs_gen_chk.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// This module generates or checks a PRBS pattern
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// See "xapp884" appnote for more info
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// Set paramaters for compliance to ITU-T Recommendation O.150 Section 5
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//--------------------------------- ------------------------------------------
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// POLY_LEN POLY_TAP INV_PATTERN | nbr of bit seq. max 0 feedback
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// | stages length sequence stages
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//--------------------------------- ------------------------------------------
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// 7(non standard) 6 false | 7 127 6 6, 7
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// 9 5 false | 9 511 8 5, 9
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// 11 9 false | 11 2047 10 9,11
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// 15 14 true | 15 32767 15 14,15
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// 20 3 false | 20 1048575 19 3,20
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// 23 18 true | 23 8388607 23 18,23
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// 29 27 true | 29 536870911 29 27,29
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// 31 28 true | 31 2147483647 31 28,31
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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prbs_gen_chk #(
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.WIDTH( 32 ),
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.CHK_MODE( 0 ),
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.INV_PATTERN( 1 ),
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.POLY_LEN( 31 ),
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.POLY_TAP( 28 )
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) prbs1 (
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.clk( clk ),
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.nrst( nrst ),
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.en( 1'b1 )
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.data_in( 0 ),
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.data_out( d[31:0] )
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)
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--- INSTANTIATION TEMPLATE END ---*/
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module prbs_gen_chk #( parameter
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WIDTH = 32, // data_in, data_out port width
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CHK_MODE = 0, // 0 - module is a gen
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// 1 - module is a chk
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INV_PATTERN = 1, // invert PRBS bit-wise
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POLY_LEN = 31, // generator polynomial length
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POLY_TAP = 28 // generator polynomial tap
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)(
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input clk,
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input nrst,
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input en,
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input [(WIDTH-1):0] data_in, // CHK_MODE: data to be checked
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// ~CHK_MODE: inject error
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output logic [(WIDTH-1):0] data_out = {WIDTH{1'b1}}
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// CHK_MODE: error found (checker), LSB is the oldest received bit
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// ~CHK_MODE: generated prbs pattern, LSB is the oldest-generated bit
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);
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// considering inversion
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logic [(WIDTH-1):0] data_in_i;
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assign data_in_i[(WIDTH-1):0] = (INV_PATTERN)?
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(~data_in[(WIDTH-1):0]):
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(data_in[(WIDTH-1):0]);
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logic [(POLY_LEN-1):0] prbs_register = {POLY_LEN{1'b1}}; // LFSR itself
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logic [WIDTH:0][(POLY_LEN-1):0] shift_table;
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logic [(WIDTH-1):0] xor_results;
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// generating [POLY_LEN cols]x[WIDTH+1 rows] table by shifting prbs register
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genvar i;
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generate
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assign shift_table[0] = prbs_register[(POLY_LEN-1):0];
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for (i=0; i<WIDTH; i=i+1) begin : gen1
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assign xor_results[i] = shift_table[i][POLY_LEN-POLY_TAP] ^ shift_table[i][0];
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assign shift_table[i+1] = { (CHK_MODE)?(data_in_i[i]):(xor_results[i]),
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shift_table[i][(POLY_LEN-1):1] };
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end
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endgenerate
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always_ff @(posedge clk) begin
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if(~nrst) begin
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data_out[(WIDTH-1):0] <= {WIDTH{1'b1}};
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prbs_register[(POLY_LEN-1):0] <= {POLY_LEN{1'b1}};
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end else if (en) begin
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// taking new bits generated by xor operation
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data_out[(WIDTH-1):0] <= xor_results[(WIDTH-1):0] ^ data_in_i[(WIDTH-1):0];
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// storing prbs register
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prbs_register[(POLY_LEN-1):0] <= shift_table[WIDTH][(POLY_LEN-1):0];
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end
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end
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endmodule
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