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98 lines
2.4 KiB
Systemverilog
98 lines
2.4 KiB
Systemverilog
//--------------------------------------------------------------------------------
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// pulse_stretch.sv
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// Pulse stretcher/extender module
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//
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// - this implementftion uses a simple delay line or counter to stretch pulses
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// - WIDTH parameter sets output pulse width
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// - if you need variable output poulse width, see pulse_gen.sv module
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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pulse_stretch #(
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.WIDTH( 8 ),
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.USE_CNTR( 0 )
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) ps1 (
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.clk( clk ),
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.nrst( nrst ),
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.in( ),
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.out( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module pulse_stretch #( parameter
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WIDTH = 8,
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USE_CNTR = 0 // ==0 - stretcher is implemented on delay line
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// ==1 - stretcher is implemented on counter
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)(
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input clk,
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input nrst,
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input in,
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output out
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);
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localparam CNTR_W = $clog2(WIDTH+1);
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generate
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//==========================================================================
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if( WIDTH == 0 ) begin
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assign out = 0;
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//==========================================================================
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end else if( WIDTH == 1 ) begin
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assign out = in;
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//==========================================================================
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end else begin
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if( USE_CNTR == '0 ) begin
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// delay line
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logic [WIDTH-1:0] shifter = '0;
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always_ff @(posedge clk) begin
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if( ~nrst ) begin
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shifter[WIDTH-1:0] <= '0;
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end else begin
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// shifting
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shifter[WIDTH-1:0] <= {shifter[WIDTH-2:0],in};
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end // nrst
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end // always
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assign out = (shifter[WIDTH-1:0] != '0);
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end else begin
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// counter
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logic [CNTR_W-1:0] cntr = '0;
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always_ff @(posedge clk) begin
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if( ~nrst ) begin
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cntr[CNTR_W-1:0] <= '0;
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end else begin
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if( in ) begin
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// setting counter
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cntr[CNTR_W-1:0] <= CNTR_W'(WIDTH);
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end else if( out ) begin
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// decrementing counter
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cntr[CNTR_W-1:0] <= cntr[CNTR_W-1:0] - 1'b1;
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end
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end // nrst
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end // always
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assign out = (cntr[CNTR_W-1:0] != '0);
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end
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end // if WIDTH
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endgenerate
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endmodule
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