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49 lines
1.2 KiB
Systemverilog
Executable File
49 lines
1.2 KiB
Systemverilog
Executable File
//------------------------------------------------------------------------------
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// reverse_dimensions.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// "Physically" reverses dimension order in systemv_erilog 2D vector
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// Thus in[7][1] signal becomes out[1][7], in[6][10] becomes out[10][6] and vise-versa
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// Module is no doubt synthesizable, but its instance does NOT occupy any FPGA resources!
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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reverse_dimensions #(
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.D1_WIDTH( 8 ),
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.D2_WIDTH( 3 )
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) RD1 (
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.in( smth[7:0][2:0] ),
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.out( htms[2:0][7:0] ) // reversed bit order
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module reverse_dimensions #( parameter
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D1_WIDTH = 8, // first dimention width
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D2_WIDTH = 3 // second dimention width
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)(
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input [D1_WIDTH-1:0][D2_WIDTH-1:0] in,
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output logic [D2_WIDTH-1:0][D1_WIDTH-1:0] out
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);
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genvar i;
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genvar j;
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generate
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for (i = 0; i < D1_WIDTH ; i++) begin : gen_i
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for (j = 0; j < D2_WIDTH ; j++) begin : gen_j
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always_comb begin
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out[j][i] = in[i][j];
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end // always_comb
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end // for
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end // for
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endgenerate
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endmodule
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